MT8952BP1 Zarlink, MT8952BP1 Datasheet - Page 7

• Manufacturer Part Number: MT8952BP1
• Description: PB FREE HDLC CONTROLLER, PLCC
• Manufacturer: Zarlink

Order of Bit Transmission/Reception
The Least Significant Bit (LSB) corresponding to D0
on the data bus is transmitted first on the serial
output (CDSTo). On the receiving side, the first bit
received on the serial input (CDSTi) is considered as
the LSB and placed on D0 of the data bus.
Registers
There are several registers in the HDLC Protocol
Controller accessible to the associated micro-
processor via the data bus. The addresses of these
registers are given in Table 1 and their functional
details are given below.
FIFO Status Register (Read):
This register (Figure 4) indicates the status of
transmit and receive FIFOs and the received byte as
described below.
Rx Byte Status: These two bits (D7 and D6) indicate
the status of the received byte ready to be read from
the receive FIFO. The status is encoded as shown in
Table 3.
Rx FIFO Status: These bits (D5 and D4) indicate the
status of receive FIFO as given by Table 4. The Rx
FIFO status bits are not updated immediately after
an access of the Rx FIFO (a read from the
microprocessor port, or a write from the serial port),
to avoid the existence of unrecoverable error
conditions.
When in external timing mode, the MT8952B must
receive two falling edges of the clock signal at the
CKi input before the Rx FIFO status bits will be
updated. When in internal 2.048 MHz timing mode,
the MT8952B must receive two falling edges of the
C2i clock before the Rx FIFO status bits will be
D7
Status Bits
Rx Byte
D7
Status
0
0
1
1
Rx Byte
D6
D6
0
1
0
1
Figure 4 - FIFO Status Register
Table 3. Received Byte Status
D5
Rx FIFO
Status
Packet Byte
First Byte
Last Byte (Good FCS)
Last Byte (Bad FCS)
D4
D3
Tx FIFO
Status
Status
D2
LOW
D1
LOW
D0
updated. When in internal 4.096 MHz timing mode,
the MT8952B must receive four falling edges of the
C4i clock before the Rx FIFO status bit will be
updated (see the section on Receive Operation -
Normal Packets).
Tx FIFO Status: These two bits (D3 and D2) indicate
the status of transmit FIFO as shown in Table 5.
The Tx FIFO status bits are updated in the same
manner as the Rx FIFO bits, except that in external
timing mode, and in internal 2.048 Mbps timing
mode, the Tx FIFO status bits are updated after two
falling edges of the CKi or the C2i signal (see the
section on Transmit Operation - Normal Packets).
Receive Data Register (Read):
Reading the Receive Data Register (Figure 5) puts
the first byte from the receive FIFO on the data bus.
The first bit of the data received on the serial input
(CDSTi) is considered to be the LSB and is available
on D0 of the data bus.
Transmit Data Register (Write):
Writing to Transmit Data Register (Figure 6) puts the
data present on the data bus into the transmit FIFO.
The LSB (D0) is transmitted first.
RD7
D7
Status Bits
Status Bits
D5
D3
0
0
1
1
0
0
1
1
Rx FIFO
Tx FIFO
RD6
D6
D4
D2
Figure 5 - Receive Data Register
0
1
0
1
0
1
0
1
Table 5. Transmit FIFO Status
Table 4. Receive FIFO Status
RD5
D5
ISO-CMOS
Rx FIFO Empty
Less than or equal to 14 bytes
Rx FIFO Full
Greater than or equal to 15 bytes
Tx FIFO Full
Greater than or equal to 5 bytes
Tx FIFO Empty
Less than or equal to 4 bytes
RD4
D4
RD3
D3
Status
Status
RD2
D2
MT8952B
RD1
D1
RD0
D0
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