MT8952BP1 Zarlink, MT8952BP1 Datasheet - Page 12

• Manufacturer Part Number: MT8952BP1
• Description: PB FREE HDLC CONTROLLER, PLCC
• Manufacturer: Zarlink

MT8952B
microprocessor should wait for a 4/19 FULL interrupt
before writing to the Tx FIFO again.
FULL interrupt has been received, a maximum of 15
bytes should be written to the Tx FIFO, then transfer
of information to the Tx FIFO should stop and the 4/
19 FULL interrupt should be waited for once more.
The FIFO may be allowed to empty if no more
information is to be sent at the moment.
procedure should keep software independent of the
frequency of the CKi signal.
Transmit Underrun:
A transmit underrun occurs when the last byte
loaded into the transmit FIFO was not ‘flagged’ with
the ‘end of packet’ (EOP) bit and there are no more
bytes in the FIFO. In such a situation, the Protocol
Controller transmits the abort sequence (eight
ONEs) and moves to the selected link channel state.
Abort Transmission:
If it is desired to abort the packet currently being
loaded into the transmit FIFO, the next byte written to
the FIFO should be ‘flagged’ to cause this to happen.
The FA bit of the Control Register must be set HIGH,
before writing the next byte into the FIFO. This bit is
cleared automatically once the byte is written to the
FIFO. When the ‘flagged’ byte reaches the bottom of
the FIFO, a frame abort sequence is sent instead of
the byte and the transmitter operation returns to
normal.
Go Ahead Transmission:
By setting the IFTF bits in the Control Register
appropriately the transmitter can be made to send
the Go Ahead sequences
Controller is not sending the packets. Since the go
ahead is defined as 011111110, contiguous 7F
appear as go aheads. As long as the IFTF bits are
set to choose go aheads, the transmitter will send
them even if data is subsequently loaded into the
FIFO. Only when the IFTF bits are set to select
something other than go aheads, will the data be
transmitted.
C-Channel Transmission:
By setting the C1EN bit in the Timing Control
Register HIGH, the information loaded in the C-
Channel Control Register can be transmitted over
channel-1 timeslot of the outgoing ST-BUS (CDSTo).
This is available only during the Internal Timing
Mode of the Protocol Controller.
3-72
ISO-CMOS
when the Protocol
When a 4/19
Hex
This
’ s
Transparent Data Transfer:
The IFTF bits in the Control Register can be set to
provide transparent data transfer disabling the
protocol functions.
generates the Flag, GA, Abort and Idle sequences
nor does it insert the zeros and calculate the FCS .
It operates in both timing modes in bytewide manner
and transmits data serially on CDSTo. If the Protocol
Controller is in the Internal Timing Mode and the
Timing Control bits are set to select 2, 6 or 7 bits/
frame, the corresponding least significant bits of
every byte loaded into the transmit FIFO are only
transmitted. The transparent data transfer facility is
not available when the Timing Control bits are set for
1 bit/frame. In case the FIFO is empty, the last byte
or the portion of the last byte, written to the FIFO is
transmitted repeatedly.
data transfer can be disabled immediately in
software (unlike during the transmission of packets)
using TxEN bit in the Control Register.
The operation of the transmitter is similar in the
External Timing Mode.
Receive Operation
After a reset on power up, the receive section is
disabled. Timing set up considerations are similar to
that of the transmit section. Address detection is
also disabled when a reset occurs. If address
detection is required, the Receiver Address Register
is loaded with the desired address and the RxAD bit
in the Control Register is set HIGH. The receive
section can then be enabled by RxEN bit in the
Control Register.
Normal Packets:
After initialization as explained above, the serial data
starts to be clocked in and the receiver checks for
the idle channel and flags. If an idle channel is
detected, the ‘Idle’ bit in the General Status Register
is set HIGH. Once a flag is detected, the receiver
synchronizes itself in a bytewide manner to the
incoming
resynchronizing to the flags until an incoming packet
appears. The incoming packet is examined on a bit-
by-bit basis, inserted zeros are deleted, the FCS is
calculated and the data bytes are written into the
receive FIFO. However, the FCS and other control
characters like the flag, abort etc., never appear in
the FIFO. If the address detection is enabled, the first
byte following the flag is compared to the byte in the
Receive Address Register and to All-Call address. If
a match is not found, the entire packet is ignored and
nothing is written to the FIFO. If the incoming
address byte is valid, the packet is received in
normal fashion. All the bytes written to the receive
data
stream.
The transmitter no longer
Note that the transparent
The
receiver
keeps