MT8952BP1 Zarlink, MT8952BP1 Datasheet - Page 22

• Manufacturer Part Number: MT8952BP1
• Description: PB FREE HDLC CONTROLLER, PLCC
• Manufacturer: Zarlink

MT8952B
AC Electrical Characteristics
Voltages are with respect to ground (V
† Timing is over recommended temperature & power supply voltages (V
‡ Typical figures are at 25
Note:
Note: Active Low to High impedance times are measured from the disabling signal edge to the time when V
High impedance times are measured from the disabling signal edge to the time when V
3-82
1
2
3
4
5
6
7
8
From
output
under test
Test load circuit- 1
Frame Pulse (F0i) width
Frame Pulse (F0i) setup time
Frame Pulse (F0i) hold time
CDSTo delay from clock input
CDSTi setup time
CDSTi hold time
C2i clock period
C4i clock period
the clock selected.
1. Channels 0 to 4 can only be active on CDSTi and CDSTo in the Internal Timing Mode.
2. Clock input CKi can be either of the ST-BUS clocks C2i (2.048MHz) or C4i (4.096 MHz) in the Internal Timing Mode.
3. The Frame Pulse set up and hold time measurements are to be referenced from the falling edge of C4i or the rising edge of C2i depending on
F0i
CKi
(C4i)
CKi
(C2i)
CDSTo
CDSTi
C
L
Figure 25 - Serial Port Input and Output in ST-BUS Format (Internal Timing Mode)
Characteristics
C
L
= 200 pF for
Test
point
measurements
on Data Bus
150 pF for
measurements
on CDSTo
50 pF for
others
ISO-CMOS
HIGH IMPEDANCE
°
C and are for design aid only: not guaranteed and not subject to production testing.
t
t
Ch. 31
Bit 0
SToZL
SToZH
SS
From
output
under test
) unless otherwise stated .
t
F0iS
†
Test load circuit- 2
- Serial Port in Internal Timing Mode - (Figure 25)
V
C
t
STiS
t
DD
L
F0iW
t
t
t
SToZH
Sym
SToZL
t
t
t
t
Figure 26 - Test Load Circuits
F0iW
F0iH
STiS
STiH
t C2i
t C4i
F0iS
t
F0iH
R
L
Test
point
=1kΩ
Min
400
200
50
30
20
20
65
Ch. 0
Bit 7
DD
Ch. 0
Bit 7
Typ
=5V
t
STiH
‡
±
5%, V
From
output
under test
out
t
C4i
has decreased by 0.5 volts.
Max
125
SS
=0V, T
Test load circuit - 3
Units
C
A
ns
ns
ns
ns
ns
ns
ns
ns
=–40 to 85
L
Test
point
t
C2i
out
has increased by 0.5 volts. Active High to
Ch. 0
Bit 6
R
See note 3.
See note 3.
Test load circuit 1 (Fig. 26)
Ch. 0
Bit 6
°
L
=1kΩ
C).
Test Conditions
Note: S
when measuring t
and in position B when
measuring t
note below.
S
1
1
is in position A
Ch. 0
Bit 5
PHZ
B
Ch. 0
Bit 5
A
. See
V
V
PLZ
SS
DD