PH3330L,115 NXP Semiconductors, PH3330L,115 Datasheet

MOSFET N-CH 30V 100A LFPAK

PH3330L,115

Manufacturer Part Number
PH3330L,115
Description
MOSFET N-CH 30V 100A LFPAK
Manufacturer
NXP Semiconductors
Series
TrenchMOS™r
Datasheet

Specifications of PH3330L,115

Package / Case
LFPak-4
Fet Type
MOSFET N-Channel, Metal Oxide
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
3.3 mOhm @ 25A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
100A
Vgs(th) (max) @ Id
2.15V @ 1mA
Gate Charge (qg) @ Vgs
30.5nC @ 4.5V
Input Capacitance (ciss) @ Vds
4840pF @ 12V
Power - Max
62.5W
Mounting Type
Surface Mount
Minimum Operating Temperature
- 55 C
Configuration
Single Triple Source
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.0033 Ohm @ 10 V
Drain-source Breakdown Voltage
30 V
Gate-source Breakdown Voltage
20 V
Continuous Drain Current
100 A
Power Dissipation
62500 mW
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
934058817115
PH3330L T/R
PH3330L T/R
1. Product profile
1.1 General description
1.2 Features and benefits
1.3 Applications
1.4 Quick reference data
Logic level N-channel enhancement mode Field-Effect Transistor (FET) in a plastic
package using TrenchMOS technology. This product is designed and qualified for use in
computing, communications, consumer and industrial applications only.
Table 1.
Symbol Parameter
V
I
P
Dynamic characteristics
Q
Static characteristics
R
D
DS
tot
GD
DSon
High efficiency due to low switching
and conduction losses
DC-to-DC converters
Notebook computers
PH3330L
N-channel TrenchMOS logic level FET
Rev. 02 — 22 October 2008
drain-source voltage T
drain current
total power
dissipation
gate-drain charge
drain-source
on-state resistance
Quick reference
Conditions
T
see
T
V
V
see
V
T
see
j
mb
mb
j
GS
DS
GS
≥ 25 °C; T
= 25 °C; see
Figure
Figure 13
Figure 11
= 25 °C; V
= 25 °C; see
= 12 V; see
= 4.5 V; I
= 10 V; I
1; see
j
D
≤ 150 °C
D
GS
= 25 A;
= 25 A;
Figure
Figure
Figure 2
= 10 V;
Figure 3
10;
Suitable for logic level gate drive
sources
Switched-mode power supplies
Voltage regulators
12;
Min
-
-
-
-
-
Product data sheet
Typ
-
-
-
6.9
2.3
Max
30
100
62.5
-
3.3
Unit
V
A
W
nC
mΩ

Related parts for PH3330L,115

PH3330L,115 Summary of contents

Page 1

PH3330L N-channel TrenchMOS logic level FET Rev. 02 — 22 October 2008 1. Product profile 1.1 General description Logic level N-channel enhancement mode Field-Effect Transistor (FET plastic package using TrenchMOS technology. This product is designed and qualified for ...

Page 2

... NXP Semiconductors 2. Pinning information Table 2. Pinning information Pin Symbol Description 1 S source 2 S source 3 S source 4 G gate mb D mounting base; connected to drain 3. Ordering information Table 3. Ordering information Type number Package Name Description PH3330L LFPAK plastic single-ended surface-mounted package (LFPAK); 4 leads 4 ...

Page 3

... NXP Semiconductors 120 I der (%) 100 Fig 1. Normalized continuous drain current as a function of mounting base temperature (A) Limit Fig 3. Safe operating area; continuous and peak drain currents as a function of drain-source voltage PH3330L_2 Product data sheet 03aa23 120 P der (%) 150 200 0 T (°C) mb Fig 2. ...

Page 4

... NXP Semiconductors 5. Thermal characteristics Table 5. Thermal characteristics Symbol Parameter R thermal resistance from th(j-mb) junction to mounting base 10 Z th(j-mb) (K/W) δ = 0.5 1 0.2 0.1 0. 0.02 single pulse - Fig 4. Transient thermal impedance from junction to mounting base as a function of pulse duration PH3330L_2 Product data sheet ...

Page 5

... NXP Semiconductors 6. Characteristics Table 6. Characteristics Symbol Parameter Static characteristics V drain-source (BR)DSS breakdown voltage V gate-source threshold GS(th) voltage I drain leakage current DSS I gate leakage current GSS R drain-source on-state DSon resistance R gate resistance G Dynamic characteristics Q total gate charge G(tot) Q gate-source charge GS Q pre-threshold ...

Page 6

... NXP Semiconductors Table 6. Characteristics …continued Symbol Parameter t turn-on delay time d(on) t rise time r t turn-off delay time d(off) t fall time f Source-drain diode V source-drain voltage SD t reverse recovery time rr Q recovered charge r PH3330L_2 Product data sheet Conditions = 0.5 Ω 4 5.6 Ω R G(ext ...

Page 7

... NXP Semiconductors 100 ( 4 0.2 0.4 Fig 5. Output characteristics: drain current as a function of drain-source voltage; typical values iss C (pF) C rss Fig 7. Input and reverse transfer capacitances as a function of gate-source voltage; typical values PH3330L_2 Product data sheet 003aab261 100 3 3.4 (A) 80 3.2 ...

Page 8

... NXP Semiconductors − (A) −4 10 min −5 10 − 0.5 1 1.5 Fig 9. Sub-threshold drain current as a function of gate-source voltage 2 a 1.6 1.2 0.8 0 Fig 11. Normalized drain-source on-state resistance factor as a function of junction temperature PH3330L_2 Product data sheet 003aab271 10 R DSon (mΩ) 8 typ ...

Page 9

... NXP Semiconductors GS(pl) V GS(th GS1 GS2 G(tot) Fig 13. Gate charge waveform definitions Fig 15. Source current as a function of source-drain voltage; typical values PH3330L_2 Product data sheet (pF 003aaa508 Fig 14. Input, output and reverse transfer capacitances as a function of drain-source voltage; typical values 100 I S (A) ...

Page 10

... NXP Semiconductors 7. Package outline Plastic single-ended surface-mounted package (LFPAK); 4 leads 1/2 DIMENSIONS (mm are the original dimensions) UNIT 1.20 0.15 1.10 0.50 mm 0.25 1.01 0.00 0.95 0.35 Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION IEC SOT669 Fig 16 ...

Page 11

... Document ID Release date PH3330L_2 20081022 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. PH3330L_1 20060201 PH3330L_2 Product data sheet ...

Page 12

... Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice ...

Page 13

... NXP Semiconductors 11. Contents 1 Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.1 General description . . . . . . . . . . . . . . . . . . . . . .1 1.2 Features and benefits . . . . . . . . . . . . . . . . . . . . .1 1.3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . .1 1.4 Quick reference data . . . . . . . . . . . . . . . . . . . . .1 2 Pinning information . . . . . . . . . . . . . . . . . . . . . . .2 3 Ordering information . . . . . . . . . . . . . . . . . . . . . .2 4 Limiting values Thermal characteristics . . . . . . . . . . . . . . . . . . .4 6 Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .5 7 Package outline . . . . . . . . . . . . . . . . . . . . . . . . .10 8 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . 11 9 Legal information .12 9.1 Data sheet status ...

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