PH4830L,115 NXP Semiconductors, PH4830L,115 Datasheet - Page 5

• Manufacturer Part Number: PH4830L,115
• Description: MOSFET N-CH 30V 84A LFPAK
• Manufacturer: NXP Semiconductors
• Series: TrenchMOS™r

Specifications of PH4830L,115

• Package / Case: LFPak-4
• Fet Type: MOSFET N-Channel, Metal Oxide
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 4.8 mOhm @ 25A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 84A
• Vgs(th) (max) @ Id: 2.15V @ 1mA
• Gate Charge (qg) @ Vgs: 22.9nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 2786pF @ 12V
• Power - Max: 62.5W
• Mounting Type: Surface Mount
• Minimum Operating Temperature: - 55 C
• Configuration: Single Triple Source
• Transistor Polarity: N-Channel
• Resistance Drain-source Rds (on): 4.8 mOhms
• Drain-source Breakdown Voltage: 30 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 84 A
• Power Dissipation: 62.5 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 934061157115; PH4830L T/R; PH4830L T/R

NXP Semiconductors
6. Characteristics
Table 5.
T
PH4830L_1
Product data sheet
Symbol Parameter
Static characteristics
V
V
I
I
R
R
Dynamic characteristics
Q
Q
Q
Q
Q
V
C
C
C
C
t
t
t
t
Source-drain diode
V
t
Q
DSS
GSS
d(on)
r
d(off)
f
rr
j
(BR)DSS
GS(th)
GS(pl)
SD
G
DSon
iss
oss
rss
iss
G(tot)
GS
GS1
GS2
GD
r
= 25 C unless otherwise specified.
drain-source breakdown
voltage
gate-source threshold voltage
drain leakage current
gate leakage current
gate resistance
drain-source on-state
resistance
total gate charge
gate-source charge
pre-V
post-V
gate-drain charge
gate-source plateau voltage
input capacitance
output capacitance
reverse transfer capacitance
input capacitance
turn-on delay time
rise time
turn-off delay time
fall time
source-drain voltage
reverse recovery time
recovered charge
Characteristics
GS(th)
GS(th)
gate-source charge
gate-source charge
Conditions
I
I
V
V
f = 1 MHz
V
V
I
see
V
see
V
V
R
I
I
V
D
D
D
S
S
DS
GS
GS
GS
GS
GS
DS
R
G
T
T
T
T
T
T
T
T
T
= 25 A; V
= 20 A; dI
= 250 A; V
= 1 mA; V
= 25 A; V
= 30 V
j
j
j
j
j
j
j
j
j
= 5.6
Figure 11
Figure 14
= 30 V; V
= 12 V; R
= 20 V; V
= 10 V; I
= 4.5 V; I
= 0 V; V
= 0 V; V
= 25 C
= 55 C
= 25 C
= 150 C
= 55 C
= 25 C
= 150 C
= 25 C
= 150 C
Rev. 01 — 6 September 2007
GS
DS
S
DS
DS
DS
D
/dt = 100 A/ s; V
D
GS
L
GS
and
= 25 A; see
= 12 V; V
= 0 V; see
DS
= V
= 25 A; see
= 0.5 ; V
= 12 V; f = 1 MHz;
= 0 V; f = 1 MHz
= 0 V
= 0 V
= 0 V
12
GS
; see
GS
Figure 13
GS
Figure 9
Figure 6
= 4.5 V;
Figure 6
= 4.5 V;
GS
= 0 V;
N-channel TrenchMOS logic level FET
and
and
and
10
8
8
Min
30
27
1.3
0.8
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Typ
-
-
1.7
-
-
-
-
-
0.51
3.8
6.3
5.6
22.9
9.0
5.5
3.5
5.4
2.8
2786
579
297
3300
28
43
35
19
0.85
47
17
PH4830L
© NXP B.V. 2007. All rights reserved.
Max
-
-
2.15
-
2.6
1.0
100
100
-
4.8
7.7
7.0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
5 of 12
Unit
V
V
V
V
V
nA
m
m
m
nC
nC
nC
nC
nC
V
pF
pF
pF
pF
ns
ns
ns
ns
V
ns
nC
A
A