STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 39

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

III - FUNCTIONAL DESCRIPTION (continued)
III.5.4 - SRAM interface
The SRAM space achieves 1 Mbyte max. It is
always organized in 16 bits. The structure of the
memory plane is shown in the following figures.
Because of the different chips usable, 19 address
wires and 8 NCE (Chip Enable) are necessary to
address the 1 Mbyte. The NCE selects the Most or
Least Significant Byte versus the value of A0 deliv-
ered by the P and the location of chip in the
memory space.
III.5.4.1 - 128K x 16 (up to 512K x 16) SRAM
This memory can be obtained with two 128K x 8
SRAM circuits (up to eight circuits)
The Address bits delivered by the Multi-HDLC for
128K x 8 SRAM circuits are :
ADM0/14 and ADM15/16 (17 bits) corresponding
with A1/17 delivered by the P.
Figure 25 :n x 128K x 16 SRAM Memory
III.5.4.2 - 512K x n SRAM
ADM0/16, NWE, NOE
are con necte dto each circuit
Signals
N
NCE5
NCE3
NCE1
NCE7
NCE6
NCE5
NCE4
NCE3
NCE2
NCE1
NCE0
CE7
Signals
NCE1
NCE0
Organization
7
5
3
1
DM8/15
A19
1
1
1
1
0
0
0
0
128K x 16
NCE6
NCE4
NCE2
NCE0
A18
1
1
0
0
1
1
0
0
A0 or equiv.
6
4
2
0
DM0/7
A0 or equiv.
1
0
128K x 8 circu it
1
0
1
0
1
0
1
0
The Address bits delivered by the Multi-HDLC for
512K x n SRAM circuits are :
ADM0/14 and ADM15/18 (19 bits) corresponding
with A1/19 delivered by the P.
Figure 26 :512K x 8 SRAM Circuit Memory
III.5.5 - DRAM Interface
In DRAM, the memory space can achieve up to 16
megabytes organized by 16 bits. Eleven address
wires, four NRAS and two NCAS are needed to
select any byte in the memory. One NRAS signal
selects 1 bank of 4 and the NCAS signals select the
bytes concerned by the transfer (1 or 2 selecting a
byte or a word). The DRAM memory interface is
then defined. The ”RAS only” refresh cycles will
refresh all memory locations. The refresh is pro-
grammable. The frequency of the refresh is fixed
by the memory requirements.
III.5.5.1 - 256K x n DRAM Signals
The Address bits delivered by the Multi-HDLC for
256K x n DRAM circuits are :
ADM0/8 (2 x 9 = 18 bits) corresponding with A1/18
delivered by the P.
Figure 27 : 256K x 16 DRAM Circuit Organization
ADM0/18, NWE, NOE
are conne cted to each circuit
NCE1
Signals
NRAS3
NRAS2
NRAS1
NRAS0
NCAS1
NCAS0
RAS3
RAS2
RAS1
RAS0
ADM0/8, NWE , NO E a re connected to ea ch circuit.
Organization
1
DM8/15
CAS1
A20
7
5
3
1
1
1
0
0
DM8/15
512K x 16
NCE0
A19
CAS0
1
0
1
0
6
4
2
0
DM0/7
0
256K x 16
DM0/7
A0
STLC5465B
1
0
512K x 8 circuit
6800
UDS
LDS
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