STLC5465B STMicroelectronics, STLC5465B Datasheet - Page 26

• Manufacturer Part Number: STLC5465B
• Description: Telecom ICs Multi-HDLC Sw Matrix
• Manufacturer: STMicroelectronics
• Type: Telecom IC - Variousr

Specifications of STLC5465B

• Operating Supply Voltage: 4.75 V to 5.25 V
• Operating Temperature Range: - 40 C to + 85 C
• Mounting Style: SMD/SMT
• Package / Case: PQFP-160
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STLC5465B
III - FUNCTIONAL DESCRIPTION (continued)
III.2.1.3 - Description and Functions of the
HDLC Bytes
- FLAG
- ABORT
- BIT STUFFING AND UNSTUFFING
- FRAME CHECK SEQUENCE
- ADDRESS RECOGNITION
26/101
The binary sequence 01111110marks the begin-
ning and the end of the HDLC Frame.
Note : In reception, three possible flag configura-
tions are allowed and correctly detected :
- two normal consecutive flags :
- two consecutive flags with a ”0” common :
- a global common flag : ...01111110...
this flag is the closing flag for the current frame
and the opening flag for the next frame
The binary sequence 1111111 marks an Abort
command.
In reception, seven consecutive1’s, inside a mes-
sage, are detected as an abort command and
generates an interrupt to the host.
In transmit direction, an abort is sent upon com-
mand of the micro-processor. No ending flag is
expected after the abort command.
This operation is done to avoid the confusion of
a data byte with a flag.
In transmission, if five consecutive 1’s appear in
the serial stream being transmitted,a zero isauto-
matically inserted (bit stuffing) after he fifth ”1”.
In reception, if five consecutive ”1” followed by a
zero are received, the ”0” is assumed to have
been inserted and is automatically deleted (bit
unstuffing).
TheFrame Check Sequenceiscalculatedaccording
to the recommendationQ921 of the CCITT.
In the frame, one or two bytes are transmitted to
indicate the destination of the message.
Two types of addresses are possible :
- a specific destination address
- a broadcast address.
In reception, the controller compares the receive
addresses to internal registers, which contain its
own address. 4 bits in the receive command
register (HRCR) inform the receiver of which
registers, it has to take into account for the com-
parison. The receiver can compare one or two
address bytes of the message to the specific
board address and/or the broadcast address.
For the specific destination address only, the
receiver can compare or not each bit of the two
receive address bytes to the programmable Ad-
dress Field Recognition register. An Address
...0111111001111110...
...011111101111110...
III.2.2 - CSMA/CR Capability
An HDLC channel can come in and go out by any
TDM input on the matrix. For time constraints,
direct HDLC Access is achieved by the input TDM
(DIN 8) and the output TDM (DOUT6).
In transmission, a time slot of a TDM can be shared
between different sources in Multi-point to point
configuration(differentsubscriber’sboardsforexam-
ple).The arbitrationsystem is the CSMA/CR (Carrier
Sense Multiple access with Contention Resolution).
The contention is resolved by a bus connected to
the CB pin (Contention Bus). This bus is a 2Mbit/s
wire line common to all the potential sources.
If a Multi-HDLC has obtained the access to the bus,
the data to transmit is sent simultaneouslyon the CB
line and the outputTDM. Theresult of the contention
is read backon the Echoline.If a collisionisdetected,
the transmission is stopped immediately. A conten-
tionon a bit basisis so achieved. Each message to
be sent with CSMA/CR has a priority class (PRI = 8,
10) indicated by the Transmit Descriptor and some
rules are implemented to arbitrate the access to the
line. The CSMA/CR Algorithm is given. When a re-
quest to send a message occurs, the transmitter
determines if the shared channel is free. The Multi-
HDLC listenstotheEcholine.If C or more consecutive
”1” are detected (C depending on the message’s
priority), the Multi-HDLC begins to send its message.
Eachbit sent is sampled back and compared with the
originalvalue to send. If a bit is different, the transmis-
sion is instantaneouslystopped(beforethe end ofthis
bit time) andwill restart as soon as the Multi-HDLC will
detectthat the channel is freewithout interrupting the
microprocessor.
After a successful transmission of a message, a
Field Recognition Mask register is associated to
each Address Field Recognition register; so each
received address bit can be masked or not indi-
vidually.
Theprogrammable AddressField Recognitionreg-
ister is located in the Address Field Recognition
MemoryandtheprogrammableAddressFieldRec-
ognition Mask register is located in the Address
Field Recognition Mask Memory.
Upon an address match, the address and the
data followingare written to the data buffers; upon
an address mismatch, the frame is ignored. So,
it authorizes the filtering of the messages. If no
comparison is specified, each frame is received
whatever its address field.
In Transmission, the whole of the transmit frame
is locatedin shared memory; the controller sends
the frame including the destination or broadcast
addresses.