DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 89

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 8-44. 16-Bit Mode without Byte Swap
Figure 8-45. 16-Bit Mode with Byte Swap
Clearing status latched registers on a read or write access is selectable via the GL.CR1.LSBCRE register bit.
Clearing on read clears all bits in the register, while the clear on write clears only those bits which are written with a
‘1’ when the user writes to the status latched register.
To use the Clear on Read method, the user must only read the status latched register. All bits are set to zero after
the read.
register has cleared.
To use the Clear on Write method, the user must write the register with ones in the bit locations that he desires to
clear.
that he wrote a ‘1’. See also Section
A[0]/BSWAP
A[0]/BSWAP
Note: Address 0x2B0 = 0x1234
Note: Address 0x2B0 = 0x1234
Figure 8-47
A[10:1]
D[15:0]
A[10:1]
D[15:0]
RDY
Figure 8-46
RD
WR
RDY
CS
WR
RD
CS
0x2B2 = 0x5678
0x2B2 = 0x5678
Z
Z
shows a read, a write, and then a subsequent read revealing the results of clearing of the bits
shows a read of a status latched register and another read of the same register verifying the
0x2B0
0x3412
0x2B0
0x1234
10.1.5
Z
Z
Z
Z
0x2B2
89
0x7856
0x2B2
0x5678
Z
Z