DS3181 Maxim Integrated Products, DS3181 Datasheet - Page 291

• Manufacturer Part Number: DS3181
• Description: Network Controller & Processor ICs DS3-E3 ATM-Packet PH Y with Built-in Line
• Manufacturer: Maxim Integrated Products

Specifications of DS3181

• Product: Framer
• Number Of Transceivers: 1
• Data Rate: 44.736 Mbps
• Supply Voltage (max): 3.465 V
• Supply Voltage (min): 3.135 V
• Supply Current (max): 280 mA
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Package / Case: TEBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

12.10.4 Receive G.751 E3 Register Map
The receive G.751 E3 uses eight registers.
Table 12-36. Receive G.751 E3 Framer Register Map
12.10.4.1 Register Bit Descriptions
Register Name:
Register Description:
Register Address:
Bit #
Name
Default
Bit #
Name
Default
Bit 13: Receive FEAC Data Link Source (DLS) – When 0, the receive FEAC controller will be sourced from the N
bit. When 1, the receive FEAC controller will be sourced from the A bit.
Bit 12: Manual Downstream AIS Insertion (MDAISI) – When 0, manual downstream AIS insertion is disabled.
When 1, manual downstream AIS insertion is enabled.
Bit 11: Automatic Downstream AIS Disable (AAISD) – When 0, the presence of an LOS, OOF, or AIS condition
will cause downstream AIS to be inserted. When 1, the presence of an LOS, OOF, or AIS condition will not cause
downstream AIS to be inserted.
Bit 10: Error Count Control (ECC) – When 0, framing errors will not be counted if an OOF or AIS condition is
present. When 1, framing errors will be counted regardless of the presence of an OOF or AIS condition.
Bits 9 to 8: Framing Error Count Control (FECC[1:0]) – These two bits control the type of framing error events
that are counted.
(1,3,5,7)2Ch
(1,3,5,7)3Ch
(1,3,5,7)2Ah
(1,3,5,7)2Eh
(1,3,5,7)3Ah
(1,3,5,7)3Eh
(1,3,5,7)20h
(1,3,5,7)22h
(1,3,5,7)24h
(1,3,5,7)26h
(1,3,5,7)28h
(1,3,5,7)30h
(1,3,5,7)32h
(1,3,5,7)34h
(1,3,5,7)36h
(1,3,5,7)38h
ADDRESS
00 = count OOF occurrences (counted regardless of the setting of the ECC bit).
01 = count each bit error in the FAS (up to 10 per frame).
10 = count frame alignment signal (FAS) errors (up to one per frame).
11 = reserved
Reserved
RAILE
15
0
7
0
E3G751.RSRIE1
E3G751.RSRIE2
E3G751.RFECR
E3G751.RSRL1
E3G751.RSRL2
E3G751.RSR1
E3G751.RSR2
E3G751.RCR
REGISTER
Reserved
—
—
—
—
—
—
—
—
RAILD
14
0
6
0
E3G751.RCR
E3 G.751 Receive Control Register
(1,3,5,7)20h
E3 G.751 Receive Control Register
Reserved
E3 G.751 Receive Status Register 1
E3 G.751 Receive Status Register 2
E3 G.751 Receive Status Register Latched 1
E3 G.751 Receive Status Register Latched 2
E3 G.751 Receive Status Register Interrupt Enable 1
E3 G.751 Receive Status Register Interrupt Enable 2
Reserved
Reserved
E3 G.751 Receive Framing Error Count Register
Reserved
Reserved
Reserved
Unused
Unused
RAIOD
DLS
13
0
5
0
MDAISI
RAIAD
12
0
0
4
291
REGISTER DESCRIPTION
AAISD
ROMD
11
0
3
0
ECC
LIP1
10
0
2
0
FECC1
LIP0
9
0
1
0
FRSYNC
FECC0
8
0
0
0