LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 226

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.4 (07-07-10)
13.4.1.4
BITS
31:7
4:3
6
5
2
1
0
RESERVED
Buffer Manager Interrupt (BM)
Set when any unmasked bit in the
Register (BM_IPR)
Switch Engine Interrupt (SWE)
Set when any unmasked bit in the
(SWE_IPR)
RESERVED
Port 2 MAC Interrupt (MAC_2)
Set when any unmasked bit in the MAC_IPR_2 register (see
13.4.2.44, on page
Port 1 MAC Interrupt (MAC_1)
Set when any unmasked bit in the MAC_IPR_1 register (see
13.4.2.44, on page
Port 0 MAC Interrupt (MAC_0)
Set when any unmasked bit in the MAC_IPR_0 register (see
13.4.2.44, on page
Switch Global Interrupt Pending Register (SW_IPR)
This read-only register contains the pending global interrupts for the Switch Fabric. A set bit indicates
an unmasked bit in the corresponding Switch Fabric sub-system has been triggered. All switch related
interrupts in this register may be masked via the
register. When an unmasked Switch Fabric interrupt is generated in this register, the interrupt will
trigger the
Refer to
Register #:
Chapter 5, "System Interrupts," on page 55
is triggered. This bit is cleared upon a read.
Switch Fabric Interrupt Event (SWITCH_INT)
270) is triggered. This bit is cleared upon a read.
270) is triggered. This bit is cleared upon a read.
270) is triggered. This bit is cleared upon a read.
is triggered. This bit is cleared upon a read.
0005h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Switch Engine Interrupt Pending Register
Buffer Manager Interrupt Pending
DATASHEET
226
Size:
Switch Global Interrupt Mask Register (SW_IMR)
for more information.
bit in the
Section
Section
Section
32 bits
Interrupt Status Register
TYPE
SMSC LAN9303/LAN9303i
RO
RC
RC
RO
RC
RC
RC
DEFAULT
(INT_STS).
Datasheet
0b
0b
0b
0b
0b
-
-