LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 186

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Revision 1.4 (07-07-10)
13.2.7.3
31:28
BITS
24:0
27
26
25
RESERVED
Device Ready (READY)
When set, this bit indicates that the device is ready to be accessed. Upon
power-up, nRST reset, or digital reset, the host processor may interrogate
this field as an indication that the device has stabilized and is fully active.
This bit can cause an interrupt if enabled.
Note:
AMDIX_EN Strap State Port 2
This bit reflects the state of the
the PHY. The strap value is loaded with the level of the
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by the
State (AMDIXSTATE)
Indication Register
AMDIX_EN Strap State Port 1
This bit reflects the state of the
the PHY. The strap value is loaded with the level of the
during reset and can be re-written by the EEPROM Loader. The strap value
can be overridden by the
State (AMDIXSTATE)
Indication Register
RESERVED
Hardware Configuration Register (HW_CFG)
This register allows the configuration of various hardware features.
Note: This register can be polled while the device is in the reset or not ready state
Note: In SMI mode, either half of this register can be read without the need to read the other half.
Note 13.53 The default value of this field is determined by the configuration strap auto_mdix_strap_2.
Note 13.54 The default value of this field is determined by the configuration strap auto_mdix_strap_1.
With the exception of the HW_CFG, BYTE_TEST, and
RESET_CTL registers, read access to any internal resources is
forbidden while the READY bit is cleared. Writes to any address
are invalid until this bit is set.
(READY)
interfaces are also in reset at this time.
Offset:
See
See
(Section
(Section
Section 4.2.4, "Configuration Straps," on page 45
Section 4.2.4, "Configuration Straps," on page 45
bit is cleared). Returned data will be invalid during the reset state since the serial
bits of the Port 2 PHY Special Control/Status
bits of the Port 1 PHY Special Control/Status
Auto-MDIX Control (AMDIXCTRL)
Auto-MDIX Control (AMDIXCTRL)
13.3.2.10).
13.3.2.10).
074h
DESCRIPTION
Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
auto_mdix_strap_2
auto_mdix_strap_1
DATASHEET
186
Size:
strap that connects to
strap that connects to
auto_mdix_strap_2
auto_mdix_strap_1
and
and
Auto-MDIX
Auto-MDIX
32 bits
for more information.
for more information.
TYPE
SMSC LAN9303/LAN9303i
RO
RO
RO
RO
RO
(Device Ready
Note 13.53
Note 13.54
DEFAULT
Datasheet
0b
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