LAN9303I-ABZJ SMSC, LAN9303I-ABZJ Datasheet - Page 131

• Manufacturer Part Number: LAN9303I-ABZJ
• Description: Ethernet ICs 3 Port 0/100 Ether Switch MII/RMII/Turb
• Manufacturer: SMSC

Specifications of LAN9303I-ABZJ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Small Form Factor Three Port 10/100 Managed Ethernet Switch with Single MII/RMII/Turbo MII
Datasheet
Chapter 11 General Purpose Timer & Free-Running Clock
SMSC LAN9303/LAN9303i
11.1
11.2
This chapter details the General Purpose Timer (GPT) and the Free-Running Clock.
The device provides a 16-bit programmable General Purpose Timer that can be used to generate
periodic system interrupts. The resolution of this timer is 100uS.
The GPT loads the
Purpose Timer Pre-Load (GPT_LOAD)
(GPT_CFG)
Configuration Register (GPT_CFG)
Timer Enable (TIMER_EN)
Timer Pre-Load (GPT_LOAD)
(GPT_CNT)
Purpose Timer Pre-Load (GPT_LOAD)
Enable (TIMER_EN)
Once enabled, the GPT counts down until it reaches 0000h, or until a new pre-load value is written to
the
FFFFh, asserts the
asserts the IRQ interrupt (if
Register
asserted, it can only be cleared by writing a 1 to the bit. Refer to
Timer Interrupt," on page 58
The Free-Running Clock (FRC) is a simple 32-bit up-counter that operates from a fixed 25MHz clock.
The current FRC value can be read via the
assertion of a chip-level reset, this counter is cleared to zero. On de-assertion of a reset, the counter
is incremented once for every 25MHz clock cycle. When the maximum count has been reached, the
counter rolls over to zeros. The FRC does not generate interrupts.
Note: The free running counter can take up to 160nS to clear after a reset event.
General Purpose Timer
Free-Running Clock
General Purpose Timer Pre-Load (GPT_LOAD)
(INT_STS)), and continues counting.
is also initialized to FFFFh on reset. Software can write a pre-load value into the
when the
GP Timer (GPT_INT)
General Purpose Timer Count Register (GPT_CNT)
bit is asserted).
General Purpose Timer Enable (TIMER_EN)
bit changes from asserted (1) to de-asserted (0), the
GP Timer Interrupt Enable (GPT_INT_EN)
for additional information on the GPT interrupt.
field is initialized to FFFFh. The
DATASHEET
is asserted (1). On a chip-level reset, or when the
field at any time (e.g. before or after the
field of the
interrupt status bit in the
131
Free Running 25MHz Counter Register
GP Timer (GPT_INT)
General Purpose Timer Configuration Register
field. At 0000h, the counter wraps around to
General Purpose Timer Count Register
Interrupt Status Register
bit of the
Section 5.2.4, "General Purpose
is a sticky bit. Once this bit is
with the value in the
is set in the
General Purpose Timer
General Purpose Timer
Revision 1.4 (07-07-10)
(FREE_RUN). On
General Purpose
General Purpose
Interrupt Status
(INT_STS),
General
General