LAN9217-MT SMSC, LAN9217-MT Datasheet - Page 73

• Manufacturer Part Number: LAN9217-MT
• Description: Ethernet ICs Hi Perfrm Sngl Chip Ethrnet Contrllr
• Manufacturer: SMSC
• Type: Single Chip MAC and PHY Controllerr

Specifications of LAN9217-MT

• Ethernet Connection Type: 10 Base-T, 100 Base-TX
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Product: Ethernet Controllers
• Number Of Transceivers: 1
• Standard Supported: 802.3, 802.3u
• Data Rate: 10 Mbps, 100 Mbps
• Supply Voltage (max): 3.3 V
• Supply Voltage (min): 0 V
• Supply Current (max): 69 mA
• Maximum Operating Temperature: + 70 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

16-bit High-Performance Single-Chip 10/100 Ethernet Controller with HP Auto-MDIX Support
Datasheet
SMSC LAN9217
5.3.1
5.3.2
31-16
BITS
31:24
23-15
15-0
BITS
11-9
7-5
14
13
12
8
Chip ID. This read-only field identifies this design
Chip Revision
Interrupt Deassertion Interval (INT_DEAS). This field determines the
Interrupt Request Deassertion Interval in multiples of 10 microseconds.
Setting this field to zero causes the device to disable the INT_DEAS
Interval, reset the interval counter, and issue any pending interrupts. If a
new, non-zero value is written to this field, any subsequent interrupts will
obey the new setting.
Note:
Reserved
Interrupt Deassertion Interval Clear (INT_DEAS_CLR). Writing a one
to this register clears the de-assertion counter in the IRQ Controller, thus
causing a new de-assertion interval to begin (regardless of whether or
not the IRQ Controller is currently in an active de-assertion interval).
Interrupt Deassertion Status (INT_DEAS_STS). When set, this bit
indicates that interrupts are currently in a deassertion interval, and will
not be delivered to the IRQ pin. When this bit is clear, interrupts are not
currently in a deassertion interval, and will be delivered to the IRQ pin.
Master Interrupt (IRQ_INT). This read-only bit indicates the state of the
internal IRQ line, regardless of the setting of the IRQ_EN bit, or the state
of the interrupt de-assertion function. When this bit is high, one of the
enabled interrupts is currently active.
Reserved
IRQ Enable (IRQ_EN) – This bit controls the final interrupt output to the
IRQ pin. When clear, the IRQ output is disabled and permanently
deasserted. This bit has no effect on any internal interrupt status bits.
Reserved
ID_REV—Chip ID and Revision
This register contains the ID and Revision fields for this design.
IRQ_CFG—Interrupt Configuration Register
This register configures and indicates the state of the IRQ signal.
Offset:
Offset:
This field does not apply to the PME interrupt.
DESCRIPTION
DESCRIPTION
50h
54h
DATASHEET
73
Size:
Size:
32 bits
32 bits
TYPE
R/W
R/W
TYPE
RO
RO
RO
RO
SC
SC
RO
RO
Revision 2.7 (03-15-10)
DEFAULT
DEFAULT
117Ah
0000h
0
0
0
0
0
-
-
-