SL28748ELC Silicon Laboratories Inc, SL28748ELC Datasheet - Page 6

• Manufacturer Part Number: SL28748ELC
• Description: Clock Generators & Support Products Calpella IronLake Jasper Forest IbexPk
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28748ELC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DOC#: SP-AP-0017 (Rev. AA)
Byte 3: Control Register 3
Byte 4: Control Register 4
Byte 5: Control Register 5
Byte 6: Control Register 6
Bit
Bit
Bit
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
@Pup
@Pup
@Pup
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
PLL1_SS_EN
PLL3_SS_EN
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
27MHz Bit 1
DOT96_OE
CPU1_OE
CPU0_OE
SATA_OE
SRC_OE
REF Bit1
Name
Name
Name
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
REF slew rate control
0 = High, 1 = Low
RESERVED
27MHz slew rate control
0 = High, 1 = Low
RESERVED
RESERVED
RESERVED
Output enable for DOT96
RESERVED
Output enable for SATA
0 = Output Disabled, 1 = Output Enabled
Output enable for SRC
0 = Output Disabled, 1 = Output Enabled
0 = Output Disabled, 1 = Output Enabled
Output enable for CPU1
0 = Output Disabled, 1 = Output Enabled
Output enable for CPU0
0 = Output Disabled, 1 = Output Enabled
Enable PLL1s spread modulation,
0 = Spread Disabled, 1 = Spread Enabled
Enable PLL3s spread modulation
0 = Spread Disabled, 1 = Spread Enabled
(see Byte 13 for Slew Rate Bit 0 and Bit 2)
(see Byte 13 for Slew Rate Bit 0 and Bit 2)
Description
Description
Description
SL28748
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