SL28748ELC Silicon Laboratories Inc, SL28748ELC Datasheet - Page 3

• Manufacturer Part Number: SL28748ELC
• Description: Clock Generators & Support Products Calpella IronLake Jasper Forest IbexPk
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28748ELC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DOC#: SP-AP-0017 (Rev. AA)
EProClock
EProClock
clock. The EProClock
promptly achieve optimum compliance and clock signal
integrity; historically, attainable typically through device and/or
board redesigns.
EProClock
hard coded.
Features:
- > 4000 bits of configurations
- Can be configured through SMBus or hard coded
- Custom frequency sets
Frequency Select Pin (FS)
Frequency Select Pin FS
Apply the appropriate logic levels to FS inputs before
CKPWRGD assertion to achieve host clock frequency
selection. When the clock chip sampled HIGH on CKPWRGD
and indicates that VTT voltage is stable then FS input values
are sampled. This process employs a one-shot functionality
and once the CKPWRGD sampled a valid HIGH, all other FS,
and CKPWRGD transitions are ignored except in test mode.
Serial Data Interface
To enhance the flexibility and function of the clock synthesizer,
a two-signal serial interface is provided. Through the Serial
Data Interface, various device functions, such as individual
clock output buffers are individually enabled or disabled. The
registers associated with the Serial Data Interface initialize to
their default setting at power-up. The use of this interface is
optional. Clock device register changes are normally made at
.
Table 1. Command Code Definition
Table 2. Block Read and Block Write Protocol
(6:0)
Bit
18:11
27:20
FS
7
Bit
8:2
0
1
10
19
28
1
9
0 = Block read or block write operation, 1 = Byte read or byte write operation
Byte offset for byte read or byte write operation. For block read or block write operations, these bits should be '0000000'
®
®
technology can be configured through SMBus or
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Byte Count–8 bits
Acknowledge from slave
is the world’s first non-volatile programmable
133MHz
100MHz
®
CPU
Programmable Technology
Block Write Protocol
®
technology allows board designer to
Power On
Default
Description
100MHz
SRC
100MHz
SATA
Description
DOT96
96MHz
- Differential skew control on true or compliment or both
- Differential duty cycle control on true or compliment or both
- Differential amplitude control
- Differential and single-ended slew rate control
- Program Internal or External series resistor on single-ended
clocks
- Program different spread profiles
- Program different spread modulation rate
system initialization, if any are required. The interface cannot
be used during system operation for power management
functions.
Data Protocol
The clock driver serial protocol accepts byte write, byte read,
block write, and block read operations from the controller. For
block write/read operation, access the bytes in sequential
order from lowest to highest (most significant bit first) with the
ability to stop after any complete byte is transferred. For byte
write and byte read operations, the system controller can
access individually indexed bytes. The offset of the indexed
byte is encoded in the command code described in Table 1.
The block write and block read protocol is outlined in Table 2
while Table 3 outlines byte write and byte read protocol. The
slave receiver address is 11010010 (D2h).
27:21
18:11
8:2
Bit
10
19
20
1
9
Start
Slave address–7 bits
Write
Acknowledge from slave
Command Code–8 bits
Acknowledge from slave
Repeat start
Slave address–7 bits
27MHz
27MHz
Block Read Protocol
14.318MHz
REF
Description
SL28748
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