SL28748ELC Silicon Laboratories Inc, SL28748ELC Datasheet - Page 5

• Manufacturer Part Number: SL28748ELC
• Description: Clock Generators & Support Products Calpella IronLake Jasper Forest IbexPk
• Manufacturer: Silicon Laboratories Inc

Specifications of SL28748ELC

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DOC#: SP-AP-0017 (Rev. AA)
Control Registers
Byte 0: Control Register 0
Byte 1: Control Register 1
Byte 2: Control Register 2
Byte 3: Control Register 3
Bit
Bit
Bit
Bit
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
4
3
2
1
0
7
6
5
@Pup
@Pup
@Pup
@Pup
HW
0
1
0
0
0
0
1
1
0
0
0
0
1
0
1
1
1
1
1
1
1
1
1
1
1
1
SRC_Main_SEL
PLL1_SS_DC
PLL3_SS_DC
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
PD_Restore
PLL3_CFB3
PLL3_CFB2
PLL3_CFB1
PLL3_CFB0
SATA_SEL
iAMT_EN
REF_OE
Name
Name
Name
Name
FS
CPU Frequency Select Bit, set by HW
0 = 133MHz, 1= 100MHz
RESERVED
RESERVED
iAMT Enable
0 = Legacy Mode, 1 = iAMT Enabled
RESERVED
Select source for SRC clock
0 = SRC_MAIN = PLL1, PLL3_CFG Table applies
1 = SRC_MAIN = PLL3, PLL3_CFG Table does not apply
Select source of SATA clock
Save configuration when PD# is asserted
RESERVED
Select for down or center SS
0 = Down spread, 1 = Center spread
Select for down or center SS
0 = Down spread, 1 = Center spread
CFB Bit [4:1] only applies when SRC_Main_SEL = 0 (Byte 0, bit 2 =0)
See Table 4 on page 9 for Configuration.
RESERVED
Output enable for REF
0 = Output Disabled, 1 = Output Enabled
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
0 = SATA = SRC_MAIN, 1= SATA = PLL4
0 = Config. cleared, 1 = Config. saved
Description
Description
Description
Description
SL28748
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