ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 36

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
IEEE Standard 1149.1 Interface (JTAG)
Serial Port Programming Interface Communication with the ispClock5600 is facilitated via an IEEE 1149.1 test
access port (TAP). It is used by the ispClock5600 both as a serial programming interface, and for boundary scan
test purposes. A brief description of the ispClock5600 JTAG interface follows. For complete details of the reference
specification, refer to the publication, Standard Test Access Port and Boundary-Scan Architecture, IEEE Std.
1149.1-1990 (which now includes IEEE Std. 1149.1a-1993).
Overview
An IEEE 1149.1 test access port (TAP) provides the control interface for serially accessing the digital I/O of the
ispClock5600. The TAP controller is a state machine driven with mode and clock inputs. Given in the correct
sequence, instructions are shifted into an instruction register which then determines subsequent data input, data
output, and related operations. Device programming is performed by addressing the configuration register, shifting
data in, and then executing a program configuration instruction, after which the data is transferred to internal
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are defined that access all data registers and perform other internal control operations. For compatibility between
compliant devices, two data registers are mandated by the IEEE 1149.1 specification. Others are functionally spec-
ified, but inclusion is strictly optional. Finally, there are provisions for optional data registers defined by the manu-
facturer. The two required registers are the bypass and boundary-scan registers. Figure 30 shows how the
instruction and various data registers are organized in an ispClock5600.
Figure 30. ispClock5600 TAP Registers
TAP Controller Specifics
The TAP is controlled by the Test Clock (TCK) and Test Mode Select (TMS) inputs. These inputs determine whether
an Instruction Register or Data Register operation is performed. Driven by the TCK input, the TAP consists of a
small 16-state controller design. In a given state, the controller responds according to the level on the TMS input as
shown in Figure 31. Test Data In (TDI) and TMS are latched on the rising edge of TCK, with Test Data Out (TDO)
becoming valid on the falling edge of TCK. There are six steady states within the controller: Test-Logic-Reset, Run-
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CMOS cells. It is these non-volatile cells that store the configuration or the ispClock5600. A set of instructions
TDI
TEST ACCESS PORT (TAP)
INSTRUCTION REGISTER (8 BITS)
ADDRESS REGISTER (10 BITS)
TCK
IDCODE REGISTER (32 BITS)
B-SCAN REGISTER (56 BITS)
BYPASS REGISTER (1 BIT)
DATA REGISTER (90 BITS)
UES REGISTER (32 BITS)
LOGIC
TMS
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OUTPUT
LATCH
TDO
ispClock5600 Family Data Sheet
NON-VOLATILE
MEMORY
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2
CMOS