ISPPAC-CLK5620V-01TN100I Lattice, ISPPAC-CLK5620V-01TN100I Datasheet - Page 22

• Manufacturer Part Number: ISPPAC-CLK5620V-01TN100I
• Description: Clock Drivers & Distribution PROGRAMMABLE ZERO DELAY CL GEN
• Manufacturer: Lattice
• Type: Zero Delay Programmable PLL Clock Generatorr

Specifications of ISPPAC-CLK5620V-01TN100I

• Max Input Freq: 320 MHz
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Supply Voltage (max): 3.6 V
• Supply Voltage (min): 3 V
• Maximum Operating Temperature: + 85 C
• Package / Case: TQFP-100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
One important point to note is that the termination supplies must have low impedance and be able to both source
and sink current without experiencing fluctuations. These requirements generally preclude the use of a resistive
divider network, which has an impedance comparable to the resistors used, or of commodity-type linear voltage
regulators, which can only source current. The best way to develop the necessary termination voltages is with a
regulator specifically designed for this purpose. Because SSTL and HSTL logic is commonly used for high-perfor-
mance memory busses, a suitable termination voltage supply is often already available in the system.
Figure 15. SSTL2, SSTL3, HSTL Receiver Configuration
VTT
Signal In
VREF IN
REFVTT
REFA+
REFA-
ispClock5600
50
CLOSED
22
OPEN
Differential
Receiver
ispClock5600 Family Data Sheet