CS493263-CLZ Cirrus Logic Inc, CS493263-CLZ Datasheet - Page 54

• Manufacturer Part Number: CS493263-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493263-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.
In this section the process of booting and
downloading to the CS493XX will be covered as
well as how to perform a soft reset. Host boot and
autoboot and reset are covered in this section.
8.1. Host Boot
A flow diagram of a typical serial download
sequence and a typical
sequence
pseudocode representing a download sequence
from
pseudocode is written in a general sense where
function calls are made to Write_* and Read_*.
The * can be replaced by I
download sequence, and INTEL or MOTO for the
parallel download sequence, depending on the
mode of host communication. For each case the
general download algorithm is the same.
The
accomplished with RESET (pin 36), and the
communication pins discussed in
“Control” on page
Figure 33. Typical Serial Boot and Download
Procedure,
and Download Procedure, illustrate typical boot
and download procedures. When reading in serial
mode, you must check that INTREQ is low to start
reading. Similarly, in parallel mode you must check
HOUTRDY.
Table 9
Table 10
mnemonic and actual hex value. These messages
will be used in the boot sequence.
Hardware configuration messages are used to
define the behavior of the DSP’s audio ports. A
more detailed description of the different hardware
configurations can be found in the
“Hardware Configuration” on page
The software configuration messages are specific
to each application. The application code user’s
guide for each application provides a list of all
pertinent configuration messages. Writing the
KICKSTART message to the CS493XX begins the
audio decode process. The KICKSTART message
will also be described in the user’s guide for each
54
BOOT PROCEDURE & RESET
download
the
defines the boot write messages and
defines the boot read messages in
and Figure 34. Typical Parallel Boot
will
programmers
be
and
36. The flow diagrams in
presented,
2
boot
C or SPI for the serial
parallel download
perspective.
74.
procedure
as
Section 11,
Section 6,
well
The
as
is
application. Until the KICKSTART has been sent,
the decoder is in a wait state.
8.1.1. Serial Download Sequence
The following is a detailed description of a serial
download sequence for the CS493XX.
1) A download sequence is started when the host
2) The host should then send the boot message
3) If
4) If initialization fails, the CS493XX sends out an
issues a hard reset and holds the mode pins
appropriately (WR, RD, and PSEL).
DOWNLOAD_BOOT (0x000004). This causes
the CS493XX to initialize itself for download.
CS493XX sends out the boot message
BOOT_START (0x01) and the host should
proceed to step 5.
INIT_FAILURE boot message byte (0xFD or
0xFE),
BOOT_ERROR byte (0xFA or 0xFC) and spins
BOOT_SUCCESS_RECEIVED
Note: When reading from the chip in a serial
communication mode, the host must wait for the
interrupt request (INTREQ) to fall before
starting the read cycle.
APPLICATION_FAILURE
the
DOWNLOAD_BOOT
Table 10. Boot Read Messages
BAD_CHECKSUM
BOOT_SUCCESS
Table 9. Boot Write Messages
BOOT_ERROR
BOOT_ERROR
SOFT_RESET
INVALID_MSG
BOOT_START
INIT_FAILURE
INIT_FAILURE
MNEMONIC
initialization
INVALID_MSG
RESERVED
RESERVED
MNEMONIC
CS49300 Family DSP
was
byte
successful
(0xFB),
0x000001
0x000002
0x000003
0x000004
0x000005
VALUE
VALUE
DS339F7
0xFC
0xFA
0xFB
0xFD
0xFE
0xFF
0x01
0x02
0xF0
the
or