CS493263-CLZ Cirrus Logic Inc, CS493263-CLZ Datasheet - Page 36

• Manufacturer Part Number: CS493263-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493263-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

6.
Control of the CS493XX can be accomplished
through one of four methods. The CS493XX
supports I
addition the CS493XX supports both a Motorola
and Intel byte wide parallel host control mode. Only
one of the four communication modes can be
selected for control. The states of the RD, WR, and
PSEL pins are sampled at the rising edge of
RESET to determine the interface type as shown in
Table
Whichever host communication mode is used, host
control of the CS493XX is handled through the
application
Configuration and control of the CS493XX decoder
and its peripherals are indirectly executed through
a
downloaded application code. In other words
successful
accomplished by following the low level hardware
communication format and high level messaging
protocol. The specifications of the messaging
protocol can be found in any of the software user’s
guides.
Only the subsection describing the communication
mode being used needs to be read by the system
designer.
6.1. Serial Communication
The CS493XX has a serial control port that
supports
communication.
The
communication mode in more detail. Flow
diagrams will illustrate read and write cycles.
Timing diagrams will be shown to demonstrate
relative edge positions of signal transitions for read
and write operations.
36
(Pin 5)
RD
1
1
0
1
messaging
CONTROL
2.
following
2
(Pin 4)
C
both
WR
®
1
1
1
0
software
communication
Table 2. Host Modes
and SPI serial communication. In
protocol
sections
SPI
(Pin 19)
PSEL
1
0
X
X
running
and
supported
Host Interface Mode
will
I
8-bit Motorola
can
2
C
Serial I
on
8-bit Intel
Serial SPI
explain
®
the
forms
only
2
C
by
®
®
®
DSP.
each
the
be
of
6.1.1. SPI Communication
SPI
accomplished with 5 communication lines: chip
select, serial control clock, serial data in, serial
data out and an interrupt request line to signal that
the DSP has data to transmit to the host.
shows the mnemonic, pin name, and pin number of
each of these signals on the CS493XX.
6.1.1.1. Writing in SPI
When writing to the device in SPI the same
protocol will be used whether writing a byte, a
message or even an entire executable download
image. The examples shown in this document can
be expanded to fit any write situation.
"SPI Write Flow Diagram" on page 37
typical write sequence:
The following is a detailed description of an SPI
write sequence with the CS493XX.
1) An SPI transfer is initiated when chip select
2) This is followed by a 7-bit address and the
3) The host should then clock data into the device
Interrupt Request
Serial Data Out
(CS) is driven low.
read/write bit set low for a write. The address
for the CS493XX defaults to 0000000b. It is
necessary to clock this address in prior to any
transfer in order for the CS493XX to accept the
write. In other words a byte of 0x00 should be
clocked into the device preceding any write.
The 0x00 byte represents the 7 bit address
0000000b, and the least significant bit set to 0
to designate a write.
most significant bit first, one byte at a time. The
data byte is transferred to the DSP on the
falling edge of the eighth serial clock. For this
reason, the serial clock should be default low
so that eight transitions from low to high to low
will occur for each byte.
Serial Data In
Serial Clock
Chip Select
Mnemonic
communication
Table 3. SPI Communication Signals
CS49300 Family DSP
Pin Name
SCDOUT
INTREQ
with
SCCLK
SCDIN
CS
the
Pin Number
CS493XX
Figure 19,
18
19
20
7
6
shows a
DS339F7
Table 3
is