CS493263-CLZ Cirrus Logic Inc, CS493263-CLZ Datasheet - Page 14

• Manufacturer Part Number: CS493263-CLZ
• Description: Audio DSPs IC Multi-Standard Audio Decoder
• Manufacturer: Cirrus Logic Inc

Specifications of CS493263-CLZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

1.10. Switching Characteristics — SPI™ Control Port
Notes: 1. The specification f
14
SCCLK clock frequency
CS falling to SCCLK rising
Rise time of SCCLK line
Fall time of SCCLK lines
SCCLK low time
SCCLK high time
Setup time SCDIN to SCCLK rising
Hold time SCCLK rising to SCDIN
Transition time from SCCLK to SCDOUT valid
Time from SCCLK rising to INTREQ rising
Rise time for INTREQ
Hold time for INTREQ from SCCLK rising
Time from SCCLK falling to CS rising
High time between active CS
Time from CS rising to SCDOUT high-Z
(VA, VD[3:1] = 2.5 V ±5%; Inputs: Logic 0 = DGND, Logic 1 = VD, C
2. Data must be held for sufficient time to bridge the 50 ns transition time of SCCLK.
3. SCDOUT should not be sampled during this time period.
4. INTREQ goes high only if there is no data to be read from the DSP at the rising edge of SCCLK for the
5. If INTREQ goes high as indicated in (Note 4), then INTREQ is guaranteed to remain high until the next
6. With a 3.3k Ohm pull-up resistor this value is typically 260ns. As this pin is open drain adjusting the pull
7. This time is by design and not tested.
aware that the actual maximum speed of the communication port may be limited by the software. The
relevant application code user’s manual should be consulted for the software speed limitations.
second-to-last bit of the last byte of data during a read operation as shown.
rising edge of SCCLK. If there is more data to be read at this time, INTREQ goes active low again. Treat
this condition as a new read transaction. Raise chip select to end the current read transaction and then
drop it, followed by the 7-bit address and the R/W bit (set to 1 for a read) to start a new read transaction.
up value will affect the rise time.
sck
Parameter
indicates the maximum speed of the hardware. The system designer should be
(Note 5, 7)
(Note 1)
(Note 7)
(Note 7)
(Note 2)
(Note 3)
(Note 4)
(Note 4)
(Note 7)
L
= 20 pF)
Symbol
t
t
t
t
scdov
t
sccsh
cscdo
t
t
cdisu
f
t
t
t
t
cdih
scrh
csht
sch
scrl
sck
css
t
scl
t
t
rr
CS49300 Family DSP
r
f
Min
150
150
200
20
50
50
20
0
-
-
-
-
-
-
(Note 6)
2000
Max
200
50
50
40
20
-
-
-
-
-
-
-
-
DS339F7
Units
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns