NTMD2C02R2SG ON Semiconductor, NTMD2C02R2SG Datasheet - Page 8

• Manufacturer Part Number: NTMD2C02R2SG
• Description: MOSFET N/P-CH COMPL 20V 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of NTMD2C02R2SG

• Fet Type: N and P-Channel
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 43 mOhm @ 4A, 4.5V
• Drain To Source Voltage (vdss): 20V
• Current - Continuous Drain (id) @ 25° C: 5.2A, 3.4A
• Vgs(th) (max) @ Id: 1.2V @ 250µA
• Gate Charge (qg) @ Vgs: 20nC @ 4.5V
• Input Capacitance (ciss) @ Vds: 1100pF @ 10V
• Power - Max: 2W
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
traverse any load line provided neither rated peak current
(I
transition time (t
DM
The Forward Biased Safe Operating Area curves define
Switching between the off−state and the on−state may
0.01
100
0.1
10
) nor rated voltage (V
1
0.1
Figure 22. Maximum Rated Forward Biased
V
SINGLE PULSE
T
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
GS
C
= 25°C
V
= 20 V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
r
, t
f
) does not exceed 10 ms. In addition the
R
THERMAL LIMIT
PACKAGE LIMIT
DS(on)
Safe Operating Area
1
N−Channel
LIMIT
dc
DSS
10 ms
) is exceeded, and that the
1 ms
100 ms
10
10 ms
di/dt = 300 A/ms
Figure 21. Reverse Recovery Time (t
SAFE OPERATING AREA
C
) of 25°C.
http://onsemi.com
100
8
t, TIME
total power averaged over a complete switching cycle must
not exceed (T
in switching circuits with unclamped inductive loads. For
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
0.01
100
0.1
A power MOSFET designated E−FET can be safely used
10
1
0.1
Standard Cell Density
High Cell Density
V
SINGLE PULSE
T
C
GS
t
Figure 23. Maximum Rated Forward Biased
a
= 25°C
V
= 8 V
t
DS
rr
t
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
rr
J(MAX)
t
b
R
THERMAL LIMIT
PACKAGE LIMIT
rr
DS(on)
)
Safe Operating Area
− T
1
P−Channel
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
LIMIT
C
dc
)/(R
qJC
10 ms
).
1 ms
10
100