MMDF2C03HDR2 ON Semiconductor, MMDF2C03HDR2 Datasheet - Page 8

• Manufacturer Part Number: MMDF2C03HDR2
• Description: MOSFET N/P-CH 30V 3A 8-SOIC
• Manufacturer: ON Semiconductor

Specifications of MMDF2C03HDR2

• Fet Type: N and P-Channel
• Fet Feature: Logic Level Gate
• Rds On (max) @ Id, Vgs: 70 mOhm @ 3A, 10V
• Drain To Source Voltage (vdss): 30V
• Current - Continuous Drain (id) @ 25° C: 4.1A, 3A
• Vgs(th) (max) @ Id: 3V @ 250µA
• Gate Charge (qg) @ Vgs: 16nC @ 10V
• Input Capacitance (ciss) @ Vds: 630pF @ 24V
• Power - Max: 2W
• Mounting Type: Surface Mount
• Package / Case: 8-SOIC (3.9mm Width)
• Configuration: Dual Dual Drain
• Transistor Polarity: N and P-Channel
• Resistance Drain-source Rds (on): 0.07 Ohms
• Forward Transconductance Gfs (max / Min): 3.6 S
• Drain-source Breakdown Voltage: 30 V
• Gate-source Breakdown Voltage: +/- 20 V
• Continuous Drain Current: 4.1 A, - 3 A
• Power Dissipation: 2 W
• Maximum Operating Temperature: + 150 C
• Mounting Style: SMD/SMT
• Fall Time: 23 ns, 194 ns
• Minimum Operating Temperature: - 55 C
• Rise Time: 65 ns, 18 ns
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: MMDF2C03HDR2OSTR

the maximum simultaneous drain−to−source voltage and
drain current that a transistor can handle safely when it is
forward biased. Curves are based upon maximum peak
junction temperature and a case temperature (T
Peak repetitive pulsed power limits are determined by using
the thermal response data in conjunction with the procedures
discussed in AN569, “Transient Thermal Resistance −
General Data and Its Use.”
traverse any load line provided neither rated peak current
(I
transition time (t
total power averaged over a complete switching cycle must
not exceed (T
in switching circuits with unclamped inductive loads. For
DM
The Forward Biased Safe Operating Area curves define
Switching between the off−state and the on−state may
A power MOSFET designated E−FET can be safely used
0.01
100
0.1
) nor rated voltage (V
10
1
0.1
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
V
SINGLE PULSE
T
Figure 12. Maximum Rated Forward Biased
C
GS
= 25°C
= 20 V
J(MAX)
r
V
, t
DS
f
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
) does not exceed 10 ms. In addition the
R
THERMAL LIMIT
PACKAGE LIMIT
− T
DS(on)
Safe Operating Area
C
1
LIMIT
)/(R
N−Channel
dc
DSS
qJC
10 ms
) is exceeded, and that the
).
1 ms
100 ms
10
di/dt = 300 A/ms
Figure 11. Reverse Recovery Time (t
10 ms
SAFE OPERATING AREA
C
) of 25°C.
http://onsemi.com
MMDF2C03HD
100
t, TIME
8
reliable operation, the stored energy from circuit inductance
dissipated in the transistor while in avalanche must be less
than the rated limit and must be adjusted for operating
conditions differing from those specified. Although industry
practice is to rate in terms of energy, avalanche energy
capability is not a constant. The energy rating decreases
non−linearly with an increase of peak current in avalanche
and peak junction temperature.
drain−to−source avalanche at currents up to rated pulsed
current (I
continuous current (I
custom. The energy rating must be derated for temperature
as shown in the accompanying graph (Figure 13). Maximum
energy at currents below rated continuous I
assumed to equal the values indicated.
0.01
100
Although many E−FETs can withstand the stress of
0.1
10
1
Standard Cell Density
High Cell Density
0.1
t
V
SINGLE PULSE
T
a
Figure 12. Maximum Rated Forward Biased
C
GS
t
rr
= 25°C
DM
= 20 V
t
rr
t
b
), the energy rating is specified at rated
V
DS
rr
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
)
R
THERMAL LIMIT
PACKAGE LIMIT
DS(on)
Safe Operating Area
1
Mounted on 2″ sq. FR4 board (1″ sq. 2 oz. Cu 0.06″
thick single sided) with one die operating, 10s max.
D
LIMIT
), in accordance with industry
P−Channel
dc
10 ms
1 ms
10
100 ms
D
can safely be
100