STS9D8NH3LL STMicroelectronics, STS9D8NH3LL Datasheet

MOSFET DUAL N-CHAN 30V 9A 8-SOIC

STS9D8NH3LL

Manufacturer Part Number
STS9D8NH3LL
Description
MOSFET DUAL N-CHAN 30V 9A 8-SOIC
Manufacturer
STMicroelectronics
Series
STripFET™r
Datasheet

Specifications of STS9D8NH3LL

Fet Type
2 N-Channel (Dual)
Fet Feature
Logic Level Gate
Rds On (max) @ Id, Vgs
22 mOhm @ 4A, 10V
Drain To Source Voltage (vdss)
30V
Current - Continuous Drain (id) @ 25° C
8A, 9A
Vgs(th) (max) @ Id
1V @ 250µA
Gate Charge (qg) @ Vgs
10nC @ 4.5V
Input Capacitance (ciss) @ Vds
857pF @ 25V
Power - Max
2W
Mounting Type
Surface Mount
Package / Case
8-SOIC (3.9mm Width)
Configuration
Dual Dual Drain
Transistor Polarity
N-Channel
Resistance Drain-source Rds (on)
0.022 Ohms
Drain-source Breakdown Voltage
30 V
Gate-source Breakdown Voltage
+/- 16 V
Continuous Drain Current
8 A, 9 A
Power Dissipation
2 W
Maximum Operating Temperature
+ 150 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 55 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
497-6030-2

Available stocks

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Price
Part Number:
STS9D8NH3LL
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STS9D8NH3LL
Manufacturer:
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Features
Application
Description
This device uses the latest advanced design rules
of ST’s STrip based technology. The Q1 and Q2
transistors, show respectively, the best gate
charge and on-resistance for minimizing the
switching and conduction losses. This application
specific Power MOSFET has been designed to
replace two SO-8 packages in DC-DC converters.
Table 1.
December 2007
STS9D8NH3LL
Optimal R
Conduction losses reduced
Switching losses reduced
Switching applications
STS9D8NH3LL
Type
Order code
Device summary
DS
(on) x Qg trade-off @ 4.5V
Q
Q
1
2
V
30V
30V
DSS
< 0.022Ω
< 0.015Ω
R
low on-resistance STripFET™ Power MOSFET
DS(on)
9D8H3LL-
Dual N-channel 30 V - 0.012 Ω - 9 A - SO-8
Marking
7nC
8nC
Qg
8A
9A
I
D
Rev 3
Figure 1.
Package
SO-8
Internal schematic diagram
STS9D8NH3LL
S0-8
Tape & reel
Packaging
www.st.com
1/14
14

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STS9D8NH3LL Summary of contents

Page 1

... SO-8 packages in DC-DC converters. Table 1. Device summary Order code STS9D8NH3LL December 2007 Dual N-channel 0.012 Ω SO-8 low on-resistance STripFET™ Power MOSFET Qg I DS(on) D 7nC 8A 8nC 9A Figure 1. Marking 9D8H3LL- Rev 3 STS9D8NH3LL S0-8 Internal schematic diagram Package Packaging SO-8 Tape & reel 1/14 www.st.com 14 ...

Page 2

... Contents Contents 1 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2.1 Electrical characteristics (curves) 3 Test circuit 4 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 5 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 2/ STS9D8NH3LL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 ...

Page 3

... STS9D8NH3LL 1 Electrical ratings Table 2. Absolute maximum ratings Symbol V Drain-source voltage ( Gate- source voltage GS I Drain current (continuous Drain current (continuous 100°C C (1) I Drain current (pulsed Total dissipation at T TOT (2) E Single pulse avalanche energy AS 1. Pulse width limited by safe operating area 2. Starting ° ...

Page 4

... Parameter Test conditions I = 250 µ Max rating =Max rating DS @125° ± 250 µ 4 4 Parameter Test conditions MHz 4 (see Figure 25) STS9D8NH3LL Type Min. Typ 0.018 0.012 0.020 0.014 2 Type Min. Typ. Q 857 1 Q 1070 2 Q 147 1 Q 290 2 ...

Page 5

... STS9D8NH3LL Table 6. Switching times Symbol t d(on) Turn-on delay time t Rise time r t d(off) Turn-off delay time t Fall time f Table 7. Source drain diode Symbol I Source-drain current SD Source-drain current (1) I SDM (pulsed) (2) V Forward on voltage SD t Reverse recovery time rr Q Reverse recovery charge ...

Page 6

... Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2. Safe operating area for Q1 Figure 4. Thermal impedance for Q1 Figure 6. Output characteristics for Q1 6/14 Figure 3. Safe operating area for Q2 Figure 5. Thermal impedance for Q2 Figure 7. Output characteristics for Q2 STS9D8NH3LL ...

Page 7

... STS9D8NH3LL Figure 8. Transfer characteristics for Q1 Figure 10. Static drain-source on resistance for Q1 Figure 12. Normalized BV for Q1 Figure 9. Figure 11. Static drain-source on resistance vs temperature Figure 13. Normalized BV DSS Electrical characteristics Transfer characteristics for Q2 for Q2 vs temperature DSS for Q2 7/14 ...

Page 8

... Electrical characteristics Figure 14. Gate charge vs gate-source voltage for Q1 Figure 16. Capacitance variations for Q1 Figure 18. Normalized gate threshold voltage vs temperature for Q1 8/14 Figure 15. Gate charge vs gate-source voltage for Q2 Figure 17. Capacitance variations for Q2 Figure 19. Normalized gate threshold voltage vs temperature for Q2 STS9D8NH3LL ...

Page 9

... STS9D8NH3LL Figure 20. Normalized on resistance vs temperature for Q1 Figure 22. Source-drain diode forward characteristics for Q1 Electrical characteristics Figure 21. Normalized on resistance vs temperature for Q2 Figure 23. Source-drain diode forward characteristics for Q2 9/14 ...

Page 10

... Test circuit Figure 24. Switching times test circuit for resistive load Figure 26. Test circuit for inductive load switching and diode recovery times Figure 28. Unclamped inductive waveform 10/14 Figure 25. Gate charge test circuit Figure 27. Unclamped Inductive load test circuit Figure 29. Switching time waveform STS9D8NH3LL ...

Page 11

... STS9D8NH3LL 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect. The category of second level interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label ...

Page 12

... STS9D8NH3LL inch MIN. TYP. MAX. 0.068 0.003 0.009 0.064 0.025 0.033 0.013 0.018 0.007 0.010 0.010 0.019 0.188 0.196 0.228 0.244 ...

Page 13

... STS9D8NH3LL 5 Revision history Table 8. Document revision history Date 05-Jan-2007 06-Mar-2007 10-Dec-2007 Revision 1 First release 2 Some value changed on 3 Added E value on AS Revision history Changes Table 4 (R for Q2) DS(on) Table 2: Absolute maximum ratings 13/14 ...

Page 14

... Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America 14/14 Please Read Carefully: © 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies www.st.com STS9D8NH3LL ...

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