MT9M001C12STM Aptina LLC, MT9M001C12STM Datasheet - Page 11

• Manufacturer Part Number: MT9M001C12STM
• Description: SENSOR IMAGE MONO CMOS 48-LCC
• Manufacturer: Aptina LLC
• Type: CMOS Imagingr

Specifications of MT9M001C12STM

• Pixel Size: 5.2µm x 5.2µm
• Active Pixel Array: 1280H x 1024V
• Frames Per Second: 30
• Voltage - Supply: 3 V ~ 3.6 V
• Package / Case: 48-CLCC
• Sensor Image Color Type: Monochrome
• Sensor Image Size: 1280x1024Pixels
• Operating Supply Voltage (min): 3V
• Operating Supply Voltage (typ): 3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Temp Range: 0C to 70C
• Package Type: CLCC
• Operating Temperature Classification: Commercial
• Mounting: Surface Mount
• Pin Count: 48
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 557-1151; Q3930625; Q3990821

Serial Bus Description
Protocol
Sequence
Bus Idle State
Start Bit
PDF: 09005aef81c2856f/Source: 09005aef80a3e031
MT9M001_DS_2.fm - Rev. F 5/06 EN
Registers are written to and read from the MT9M001 through the two-wire serial inter-
face bus. The sensor is a two-wire serial interface slave and is controlled by the serial
clock (SCLK), which is driven by the serial interface master. Data is transferred into and
out of the MT9M001 through the serial data (S
3.3V off-chip by a 1.5KΩ resistor. Either the slave or master device can pull the S
down—the serial interface protocol determines which device is allowed to pull the
S
The two-wire serial interface defines several different transmission codes, as follows:
• a start bit
• the slave device eight-bit address
• a(an) (no) acknowledge bit
• an 8-bit message
• a stop bit
A typical read or write sequence begins by the master sending a start bit. After the start
bit, the master sends the slave device's eight-bit address. The last bit of the address
determines if the request will be a read or a write, where a “0” indicates a write and a “1”
indicates a read. The slave device acknowledges its address by sending an acknowledge
bit back to the master.
If the request was a write, the master then transfers the 8-bit register address to which a
write should take place. The slave sends an acknowledge bit to indicate that the register
address has been received. The master then transfers the data eight bits at a time, with
the slave sending an acknowledge bit after each eight bits. The MT9M001 uses 16-bit
data for its internal registers, thus requiring two 8-bit transfers to write to one register.
After 16 bits are transferred, the register address is automatically incremented, so that
the next 16 bits are written to the next register address. The master stops writing by
sending a start or stop bit.
A typical read sequence is executed as follows. First the master sends the write-mode
slave address and 8-bit register address, just as in the write request. The master then
sends a start bit and the read-mode slave address. The master then clocks out the
register data eight bits at a time. The master sends an acknowledge bit after each 8-bit
transfer. The register address is auto-incremented after every 16 bits is transferred. The
data transfer is stopped when the master sends a no-acknowledge bit.
The bus is idle when both the data and clock lines are HIGH. Control of the bus is initi-
ated with a start bit, and the bus is released with a stop bit. Only the master can generate
the start and stop bits.
The start bit is defined as a HIGH-to-LOW transition of the data line while the clock line
is HIGH.
DATA
line down at any given time.
MT9M001: 1/2-Inch Megapixel Digital Image Sensor
11
Micron Technology, Inc., reserves the right to change products or specifications without notice.
DATA
) line. The S
Serial Bus Description
©2004 Micron Technology, Inc. All rights reserved.
DATA
line is pulled up to
DATA
line