AD8340ACPZ-WP Analog Devices Inc, AD8340ACPZ-WP Datasheet - Page 14

• Manufacturer Part Number: AD8340ACPZ-WP
• Description: IC MOD VECT 700-1000MHZ 24-LFCSP
• Manufacturer: Analog Devices Inc

Specifications of AD8340ACPZ-WP

• Function: Vector, Modulator
• Lo Frequency: 700MHz ~ 1GHz
• Rf Frequency: 700MHz ~ 1GHz
• P1db: 11dBm
• Noise Floor: -149dBm/Hz
• Current - Supply: 150mA
• Voltage - Supply: 4.75 V ~ 5.25 V
• Test Frequency: 880MHz
• Package / Case: 24-VFQFN, CSP Exposed Pad
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

AD8340
INTERFACING TO HIGH SPEED DACs
The AD977x family of dual DACs is well suited for driving the
I and Q vector controls of the AD8340. While these inputs can
in general be driven by any DAC, the differential outputs and
bias level of the Analog Devices TxDAC® family allow for a
direct connection between DAC and modulator.
The AD977x family of dual DACs has differential current
outputs. The full-scale current is user programmable and is
usually set to 20 mA, that is, each output swings from 0 mA
to 20 mA.
The basic interface between the AD9777 DAC outputs and the
AD8340 I and Q inputs is shown in Figure 33. The resistors R1
and R2 set the dc bias level according to the equation:
For example, if the full-scale current from each output is 20 mA,
each output will have an average current of 10 mA. Therefore,
to set the bias level to the recommended 0.5 V, R1 and R2
should be set to 50 Ω each. R1 and R2 should always be equal.
If R3 is omitted, this results in an available swing from the DAC
of 2 V p-p differential, which is twice the maximum voltage
range required by the AD8340. DAC resolution can be
maximized by adding R3, which scales down this voltage
according to the following equation:
AD9777
Bias Level = Average Output Current × R1
2
Full
I
I
I
I
OUTB1
OUTB2
OUTA1
OUTA2
×
I
MAX
−
Scale
Figure 33. Basic AD9777 to AD8340 Interface
(
R1
Swing
R1
R2
R1
R2
(
R2
+
=
R3
)
LOW-PASS
OPTIONAL
LOW-PASS
OPTIONAL
)
FILTER
FILTER
×
⎛
⎜
⎝
1
−
R2
R2
+
R3
R3
R3
⎞
⎟
⎠
IBBP
IBBM
QBBP
QBBM
AD8340
Rev. B | Page 14 of 20
Figure 34 shows the relationship between the value of R3 and
the peak baseband voltage with R1 and R2 equal to 50 Ω. Figure 34
shows that a value of 100 Ω for R3 provides a peak-to-peak
swing of 1 V p-p differential into the AD8340 I and Q inputs.
When using a DAC, low-pass image reject filters are typically
used to eliminate the Nyquist images produced by the DAC.
They also provide the added benefit of eliminating broadband
noise that might feed into the modulator from the DAC.
CDMA2000 APPLICATION
To test the compliance to the CDMA2000 base station standard,
a single-carrier CDMA2000 test model signal (forward pilot, sync,
paging, and six traffic as per 3GPP2 C.S0010-B, Table 6.5.2.1)
was applied to the AD8340. A cavity-tuned filter was used to
reduce noise from the signal source being applied to the device.
The 4.6 MHz pass band of this filter is apparent in the
subsequent spectral plots (see Figure 35 to Figure 38).
Figure 35 shows a plot of the spectrum of the output signal
under nominal conditions. P
= 0.353 V, that is, VIBBP − VIBBM = VQBBP − VQBBM =
0.353 V. Adjacent channel power is measured in 30 kHz
resolution bandwidth at 750 kHz and 1.98 MHz carrier offset.
Noise floor is measured at ±4 MHz carrier offset.
1.15
1.13
1.10
1.08
1.05
1.02
1.00
0.97
0.95
0.92
0.90
0.88
0.85
0.82
0.80
0.77
0.75
0.72
0.70
50 55 60 65 70 75 80 85 90
Figure 34. Peak-to-Peak DAC Output Swing vs.
Swing Scaling Resistor R3 (R1 = R2 = 50 Ω)
OUT
R3
is equal to −5 dBm and V
95
100 105
110
115 120
125
130
I
= V
Q