LH7A404N0F092B3;55 NXP Semiconductors, LH7A404N0F092B3;55 Datasheet - Page 35

• Manufacturer Part Number: LH7A404N0F092B3;55
• Description: LH7A404N0F092B3/LFBGA324/TRAYD
• Manufacturer: NXP Semiconductors
• Series: BlueStreak ; LH7Ar

Specifications of LH7A404N0F092B3;55

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, IrDA, Microwire, MMC, PS2, SmartCard, SPI, SSI, SSP, UART/USART, USB
• Peripherals: AC'97, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 64
• Program Memory Type: ROMless
• Ram Size: 80K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 3.6 V
• Data Converters: A/D 9x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 324-LFBGA
• Processor Series: LH7A4
• Core: ARM9TDMI
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 568-4304 - BOARD EVAL FOR LH7A404
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-4336; 935285071557; LH7A404N0F092B3

32-Bit System-on-Chip
AC Specifications
tions following an internal reference clock signal.
The illustration in Figure 7 represents all cases of
these sets of measurement parameters.
• HCLK, internal System Bus clock (‘C’ in timing data)
• PCLK, the Peripheral Bus clock
• SSPCLK, the Synchronous Serial Port clock
• UARTCLK, the UART Interface clock
• LCDDCLK, the LCD Data clock from the
• ACBITCLK, the AC97 and ACI clock
• SCLK, the Synchronous Memory clock.
point of the clock to the 50 % point of the signal.
Preliminary data sheet
LCD Controller
All signals described in Table 12 relate to transi-
The reference clock signals in this design are:
All signal transitions are measured from the 50 %
REFERENCE
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
CLOCK
Figure 7. LH7A404 Signal Timing
tOVXXX
NXP Semiconductors
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 12.
amount of time the output must be held valid after the
rising edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 12.
amount of setup time the input signal must be valid after
a valid address bus, or rising edge of the peripheral
clock. Maximum requirements for tISXXX are shown in
Table 12.
amount of time the output must be held valid following
the rising edge of the reference clock signal. Minimum
requirements are shown in Table 12.
tISXXX tIHXXX
For outputs from the LH7A404, tOVXXX (e.g. tOVA)
The signal tOHXXX (e.g. tOHA) represents the
For inputs, tISXXX (e.g. tISD) represents the
The signal tIHXXX (e.g. tIHD) represents the
tOHXXX
LH7A404
LH7A404-9
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