KSZ8893MQL Micrel Inc, KSZ8893MQL Datasheet
KSZ8893MQL
Specifications of KSZ8893MQL
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KSZ8893MQL Summary of contents
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... General Description The KSZ8893MQL/MBL, a highly integrated layer 2 managed switch, is designed for low port count, cost-sensitive 10/100 Mbps switch systems. It offers an extensive feature set that includes rate limiting, tag/port-based VLAN, QoS priority, management, management information base (MIB) counters, RMII/MII/SNI, and CPU control/data interfaces to effectively address both current and emerging Fast Ethernet applications ...
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Features • Proven Integrated 3-Port 10/100 Ethernet Switch – 3rd generation switch with three MACs and two PHYs fully compliant with IEEE 802.3u standard – Non-blocking switch fabric assures fast packet delivery by utilizing an 1K MAC address lookup table ...
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... Updated ordering information Updated package information Updated default register values Updated current consumption description Changed device reference in datasheet from KS8893M to KSZ8893MQL Added repeater mode description 1.2 02/08/07 Modify Table 5. RMII Signal Connections Add TLA-6T718 to Table 16. Qualified Single Port Magnetics 1 ...
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... Contents List of Figures...................................................................................................................................... 8 List of Tables ....................................................................................................................................... 9 Pin Description and I/O Assignment of KSZ8893MQL .................................................................... 10 Ball Description and I/O Assignment of KSZ8893MBL ................................................................... 19 Pin Configuration............................................................................................................................... 26 Functional Overview: Physical Layer Transceiver .......................................................................... 28 100BASE-TX Transmit.........................................................................................................................................................28 100BASE-TX Receive ..........................................................................................................................................................28 PLL Clock Synthesizer........................................................................................................................................................28 Scrambler/De-scrambler (100BASE-TX Only) ...................................................................................................................29 100BASE-FX Operation.......................................................................................................................................................29 100BASE-FX Signal Detection............................................................................................................................................29 100BASE-FX Far-End Fault.................................................................................................................................................29 10BASE-T Transmit ...
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QoS Priority Support...........................................................................................................................................................48 Port-Based Priority..............................................................................................................................................................48 802.1p-Based Priority..........................................................................................................................................................48 DiffServ-Based Priority .......................................................................................................................................................49 Rate Limiting Support .........................................................................................................................................................49 Unicast MAC Address Filtering..........................................................................................................................................49 Configuration Interface ....................................................................................................................................................... Master Serial Bus Configuration .............................................................................................................................. Slave Serial Bus Configuration ................................................................................................................................51 SPI Slave Serial ...
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Register 18 (0x12): Port 1 Control 2 ..............................................................................................................................71 Register 34 (0x22): Port 2 Control 2 ..............................................................................................................................71 Register 50 (0x32): Port 3 Control 2 ..............................................................................................................................71 Register 19 (0x13): Port 1 Control 3 ..............................................................................................................................72 Register 35 (0x23): Port 2 Control 3 ..............................................................................................................................72 ...
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Register 114 (0x72): MAC Address Register 2 ..............................................................................................................89 Register 115 (0x73): MAC Address Register 3 ..............................................................................................................89 Register 116 (0x74): MAC Address Register 4 ..............................................................................................................89 Register 117 (0x75): MAC Address Register 5 ..............................................................................................................89 Register 118 (0x76): User Defined Register 1 ...............................................................................................................90 ...
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... Figure 4. Destination Address Lookup Flow Chart, Stage 1 ................................................................................................................ 36 Figure 5. Destination Address Resolution Flow Chart, Stage 2 ........................................................................................................... 37 Figure 6. 802.1p Priority Field Format ................................................................................................................................................. 48 Figure 7. KSZ8893MQL/MBL EEPROM Configuration Timing Diagram .............................................................................................. 50 Figure 8. SPI Write Data Cycle............................................................................................................................................................ 52 Figure 9. SPI Read Data Cycle............................................................................................................................................................ 53 Figure 10. SPI Multiple Write ............................................................................................................................................................... 53 Figure 11 ...
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... Table 12. STPID Egress Rules (Switch Port 3 to Processor)............................................................................................................... 46 Table 13. FID+DA Lookup in VLAN Mode ........................................................................................................................................... 47 Table 14. FID+SA Lookup in VLAN Mode ........................................................................................................................................... 48 Table 15. KSZ8893MQL/MBL SPI Connections .................................................................................................................................. 52 Table 16. Format of Static MAC Table (8 Entries) ............................................................................................................................... 93 Table 17. Format of Static VLAN Table (16 Entries) ............................................................................................................................ 94 Table 18. Format of Dynamic MAC Address Table (1K Entries) .......................................................................................................... 95 Table 19. Format of “ ...
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... Pin Description and I/O Assignment of KSZ8893MQL Pin Number Pin Name 1 P1LED2 2 P1LED1 3 P1LED0 Note: 1. Ipu/O = Input with internal pull-up during reset, output pin otherwise. December 2007 (1) Type Description Ipu/O Port 1 LED Indicators (apply to all modes of operation, except Repeater Mode) Ipu/O Ipu/O ...
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Pin Number Pin Name 4 P2LED2 5 P2LED1 6 P2LED0 7 DGND 8 VDDIO Note Power supply. Gnd = Ground. Ipu/O = Input with internal pull-up during reset, output pin otherwise. December 2007 (1) Type Description Ipu/O ...
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Pin Number Pin Name ADVFC 13 P2ANEN 14 P2SPD 15 P2DPX 16 P2FFC P2LED3 21 DGND 22 VDDCO 23 LEDSEL1 P1LED3 Note: 1. ...
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Pin Number Pin Name 26 RMII_EN 27 HWPOVR 28 P2MDIXDIS 29 P2MDIX 30 P1ANEN 31 P1SPD 32 P1DPX 33 P1FFC PWRDN 37 AGND 38 VDDA 39 AGND 40 MUX1 41 MUX2 Note ...
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Pin Number Pin Name 42 AGND 43 VDDA 44 FXSD1 45 RXP1 46 RXM1 47 AGND 48 TXP1 49 TXM1 50 VDDATX 51 VDDARX 52 RXM2 53 RXP2 54 AGND 55 TXM2 56 TXP2 57 VDDA 58 AGND 59 TEST1 ...
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Pin Number Pin Name 70 LEDSEL0 71 SMTXEN 72 SMTXD3 73 SMTXD2 74 SMTXD1 75 SMTXD0 76 SMTXER 77 SMTXC / REFCLK 78 DGND 79 VDDIO 80 SMRXC 81 SMRXDV 82 SMRXD3 83 SMRXD2 84 SMRXD1 85 SMRXD0 86 SCOL ...
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Pin Number Pin Name 88 SCONF1 89 SCONF0 90 DGND 91 VDDC 92 UNUSED 93 UNUSED 94 MDC 95 MDIO 96 SPIQ 97 SCL 98 SDA 99 SPIS_N Note Power supply. Gnd = Ground Input. ...
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Pin Number Pin Name 100 PS1 101 PS0 102 UNUSED 103 UNUSED Note Input. December 2007 (1) Type Description I Serial bus configuration pins to select mode of access to KSZ8893MBL internal registers. I [PS1, PS0] = ...
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Pin Number Pin Name 104 UNUSED 105 UNUSED 106 DGND 107 VDDIO 108 UNUSED 109 UNUSED 110 UNUSED 111 UNUSED 112 UNUSED 113 UNUSED 114 UNUSED 115 UNUSED 116 UNUSED 117 UNUSED 118 UNUSED 119 UNUSED 120 UNUSED 121 UNUSED ...
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Ball Description and I/O Assignment of KSZ8893MBL Ball Number Ball Name C10 P1LED2 B10 P1LED1 A10 P1LED0 Note: 1. Ipu/O = Input with internal pull-up during reset, output pin otherwise. December 2007 (1) Type Ball Function Description Ipu/O Port 1 ...
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Ball Number Ball Name C9 P2LED2 B9 P2LED1 A9 P2LED0 C8 ADVFC B8 P2ANEN December 2007 (1) Type Ball Function Description Ipu/O Port 2 LED Indicators (apply to all modes of operation, except Repeater Mode) Ipu/O Ipu/O P2LED3 P2LED2 P2LED1 ...
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Ball Number Ball Name A8 P2SPD B7 P2DPX A7 P2FFC B6 P2LED3 A6 LEDSEL1 B5 P1LED3 A5 RMII_EN B4 HWPOVR A4 P2MDIXDIS B3 P2MDIX A3 P1ANEN B2 P1SPD A2 P1DPX December 2007 (1) Type Ball Function Description Ipd 1 = ...
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Ball Number Ball Name A1 P1FFC B1 PWRDN C3 FXSD1 C1 RXP1 C2 RXM1 D1 TXP1 D2 TXM1 F2 RXM2 F1 RXP2 G2 TXM2 G1 TXP2 H2 ISET RST_N J2 LEDSEL0 K2 SMTXEN J3 SMTXD3 ...
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Ball Number Ball Name K7 SMRXD2 J8 SMRXD1 K8 SMRXD0 J9 SCOL K9 SCRS J10 SCONF1 K10 SCONF0 H10 MDC H9 MDIO G9 SPIQ G10 SCL F9 SDA F10 SPIS_N December 2007 (1) Type Ball Function Description Ipd/O Switch MII ...
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Ball Number Ball Name E9 PS1 PS0 E10 D9 TESTEN D10 SCANEN C5, D8, E8, H6, VDDC H7 C4 VDDCO December 2007 (1) Type Ball Function Description I Serial bus configuration pins to select mode of access to KSZ8893MBL internal ...
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Ball Number Ball Name E3, F3, G3 VDDA C6, C7, F8, G8, VDDIO H4 VDDATX E2 VDDARX D4, D5, D6, D7, GND E4, E5, E6, E7, F4, F5, F6, F7, G4, G5, G6, G7 D3, H3 ...
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Pin Configuration 103 UNUSED 104 UNUSED 105 UNUSED 106 DGND 107 VDDIO 108 UNUSED 109 UNUSED 110 UNUSED 111 UNUSED 112 UNUSED 113 UNUSED 114 UNUSED 115 UNUSED 116 UNUSED 117 UNUSED 118 UNUSED 119 UNUSED 120 UNUSED 121 UNUSED ...
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Ball Configuration FFC DPX PWR SPD C RXP1 RXM1 D TXP1 TXM1 VDDA VDDA RXP2 RXM2 G TXP2 TXM2 H X1 ISET LED J X2 SEL0 SM K ...
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... On the media side, the KSZ8893MQL/MBL supports IEEE 802.3 10BASE-T and 100BASE-TX on both PHY ports, and also 100BASE-FX on PHY port 1, which allows the KSZ8893MQL/MBL to be used as a media converter. Physical signal transmission and reception are enhanced through the use of patented analog circuitries that make the design more efficient and allow for lower power consumption and smaller chip die size ...
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... A far-end fault (FEF) occurs when the signal detection is logically false on the receive side of the fiber transceiver. The KSZ8893MQL/MBL detects a FEF when its FXSD1 input is between 1V and 1.8V. When a FEF is detected, the KSZ8893MQL/MBL signals its fiber link partner that a FEF has occurred by sending 84 1’s followed by a zero in the idle period between frames. ...
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... The receiver clock is maintained active during idle periods in between data reception. Power Management The KSZ8893MQL/MBL features a per-port power down mode. To save power, a PHY port that is not in use can be powered down via port control register, or MIIM PHY register. In addition, there is a full chip power down mode. When activated, the entire chip is powered down. ...
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Straight Cable A straight cable connects an MDI device to an MDI-X device MDI-X device to an MDI device. The following diagram depicts a typical straight cable connection between a NIC card (MDI) and a switch, or hub ...
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... KSZ8893MQL/MBL link partner is forced to bypass auto-negotiation, the KSZ8893MQL/MBL sets its operating mode by observing the signal at its receiver. This is known as parallel detection, and allows the KSZ8893MQL/MBL to establish link by listening for a fixed signal protocol in the absence of auto-negotiation advertisement protocol. The link up process is shown in the following flow diagram. ...
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Start Auto Negotiation Force Link Setting Yes Bypass Auto Negotiation and Set Link Mode Figure 3. Auto-Negotiation and Parallel Operation December 2007 N Parallel Operation o Attempt Auto Listen for 100BASE-TX Negotiation Idles Join Flow Link Mode Set ? Yes ...
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... The ‘11’ case, invalid test, occurs when the KSZ8893MQL/MBL is unable to shut down the link partner. In this instance, the test is not run, since it would be impossible for the KSZ8893MQL/MBL to determine if the detected signal is a reflection of the signal generated or a signal from another source. 5. Get distance to fault by concatenating register 26, bit [0] and register 27, bits [7:0] ...
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... Forwarding The KSZ8893MQL/MBL forwards packets using the algorithm that is depicted in the following flowcharts. Figure 4 shows stage one of the forwarding algorithm where the search engine looks up the VLAN ID, static table, and dynamic table for the destination address, and comes up with “port to forward 1” (PTF1). PTF1 is then further modified by spanning tree, IGMP snooping, port mirroring, and port VLAN processes to come up with “ ...
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PTF1= NULL Search complete. Get PTF1 from Static MAC Table Search complete. Get PTF1 from Dynamic MAC Table Figure 4. Destination Address Lookup Flow Chart, Stage 1 December 2007 Start - Search VLAN table NO VLAN ID - Ingress VLAN ...
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... These include framing errors, Frame Check Sequence (FCS) errors, alignment errors, and illegal size packet errors. 2. IEEE802.3x PAUSE frames KSZ8893MQL/MBL intercepts these packets and performs full duplex flow control accordingly. 3. "Local" packets Based on destination address (DA) lookup. If the destination port from the lookup table matches the port from which the packet originated, the packet is defined as " ...
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... The flow control is based on availability of the system resources, including available buffers, available transmit queues and available receive queues. The KSZ8893MQL/MBL will flow control a port that has just received a packet if the destination port resource is busy. The KSZ8893MQL/MBL issues a flow control frame (XOFF), containing the maximum pause time defined by the IEEE 802 ...
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... Note: These bits are not set as defaults, as this is not the IEEE standard. Broadcast Storm Protection The KSZ8893MQL/MBL has an intelligent option to protect the switch system from receiving too many broadcast packets. As the broadcast packets are forwarded to all ports except the source port, an excessive number of switch resources (bandwidth and available space in transmit queues) may be utilized. The KSZ8893MQL/MBL has the option to include “ ...
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... Contains two distinct groups of signals: one for transmission and the other for reception The RMII provided by the KSZ8893MQL/MBL is connected to the device’s third MAC. It complies with the RMII Specification. The following table describes the signals used by the RMII bus. Refer to RMII Specification for full detail on the signal description ...
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... The serial network interface (SNI) or 7-wire is compatible with some controllers used for network layer protocol processing. In SNI mode, the KSZ8893MQL/MBL acts like a PHY and the external controller functions as the MAC. The KSZ8893MQL/MBL can interface directly with external controllers using the 7-wire interface. These signals are divided into two groups, one for transmission and the other for reception ...
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... Data Input/Output (MDIO) Interface. This interface allows upper-layer devices to monitor and control the states of the KSZ8893MQL/MBL. An external device with MDC/MDIO capability is used to read the PHY status or configure the PHY settings. Further detail on the MIIM interface is found in Clause 22.2.4.5 of the IEEE 802.3u Specification ...
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... Repeater Mode The KSZ8893MQL/MBL supports repeater mode in 100BASE-TX Half Duplex mode. In repeater mode, all ingress packets are broadcast to the other two ports. MAC address checking and learning are disabled. Repeater mode is enabled by setting register 6 bit[7] to ‘1’. Prior to setting this bit, all three ports need to be configured to 100BASE-TX Half Duplex mode ...
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Advanced Switch Functions Spanning Tree Support To support spanning tree, port 3 is designated as the processor port. The other ports (port 1 and port 2) can be configured in one of the five spanning tree states via “transmit enable”, ...
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... MAC table lookup to determine the forwarding port(s). The KSZ8893MQL/MBL uses a non-zero “port mask” to bypass the internal MAC table lookup result, and override any port setting, regardless of port states (disable, blocking, listening, learning). The table below shows the processor to switch egress rules when dealing with STPID ...
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... Hop count limit = 1 • IPv6 next header = ( with hop-by-hop next header = 1 or 58) If the MLD option bit is set to “1”, the KSZ8893MQL/MBL traps packets with the following additional condition: • IPv6 next header = 43, 44, 50 with hop-by-hop next header = 43, 44, 50, 51, or ...
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... A packet received on port 1 is destined to port 2 after the internal lookup. The KSZ8893MQL/MBL forwards the packet to both port 2 and port 3. The KSZ8893MQL/MBL can optionally even forward “bad” received packets to the “sniffer port”. ...
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... Yes Advanced VLAN features, such as “Ingress VLAN filtering” and “Discard Non PVID packets” are also supported by the KSZ8893MQL/MBL. These features can be set on a per port basis, and are defined in register 18, 34 and 50 for ports 1, 2 and 3, respectively. QoS Priority Support The KSZ8893MQL/MBL provides Quality of Service (QoS) for applications such as VoIP and video conferencing ...
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... MAC address table is used to assign a dedicated MAC address to a specific port unicast MAC address is not recorded in the static table also not learned in the dynamic MAC table. The KSZ8893MQL/MBL is then configured with the option to either filter or forward unicast packets for an unknown MAC address. This option is enabled and configured in register 14 ...
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... C master mode by setting the KSZ8893MQL/MBL strap-in pins, PS[1:0] (pins 100 and 101, respectively) to “00”. 3. Check to ensure that the KSZ8893MQL/MBL reset signal input, RST_N (pin 67), is properly connected to the external reset source at the board level. 4. Program the desired configuration data into the EEPROM. ...
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... SPI Slave Serial Bus Configuration In managed mode, the KSZ8893MQL/MBL can be configured as a SPI slave device. In this mode, a SPI master device (external controller/CPU) has complete programming access to the KSZ8893MQL/MBL’s 142 registers. ...
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... Configure the desired register settings in the KSZ8893MQL/MBL, using the SPI write or multiple write command. 5. Read back and verify the register settings in the KSZ8893MQL/MBL, using the SPI read or multiple read command. 6. Write a ‘1’ to the “Start Switch” bit to start the KSZ8893MQL/MBL with the programmed settings. ...
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SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N SPIC SPID SPIQ WRITE COMMAND SPIS_N SPIC SPID SPIQ Byte 2 SPIS_N SPIC SPID SPIQ READ COMMAND SPIS_N ...
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... Near-end (Remote) Loopback. Far-end Loopback Far-end loopback is conducted between the KSZ8893MQL/MBL’s two PHY ports. The loopback path starts at the “Originating.” PHY port’s receive inputs (RXP/RXM), wraps around at the “loopback” PHY port’s PMD/PMA, and ends at the “Originating” PHY port’s transmit outputs (TXP/TXM). ...
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... Near-end (Remote) Loopback Near-end (Remote) loopback is conducted at either PHY port 1 or PHY port 2.of the KSZ8893MQL/MBL. The loopback path starts at the PHY port’s receive inputs (RXPx/RXMx), wraps around at the same PHY port’s PMD/PMA, and ends at the PHY port’s transmit outputs (TXPx/TXMx). ...
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MII Management (MIIM) Registers The MIIM interface is used to access the MII PHY registers defined in this section. The SPI, I interfaces can also be used to access some of these registers. The latter three interfaces use a different ...
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PHY1 Register 0 (PHYAD = 0x1, REGAD = 0x0): MII Basic Control PHY2 Register 0 (PHYAD = 0x2, REGAD = 0x0): MII Basic Control Bit Name R/W 15 Soft reset RO 14 Loopback R/W 13 Force 100 R ...
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PHY1 Register 1 (PHYAD = 0x1, REGAD = 0x1): MII Basic Status PHY2 Register 1 (PHYAD = 0x2, REGAD = 0x1): MII Basic Status Bit Name R capable RO 14 100 Full RO capable 13 100 Half RO ...
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PHY1 Register 4 (PHYAD = 0x1, REGAD = 0x4): Auto-Negotiation Advertisement Ability PHY2 Register 4 (PHYAD = 0x2, REGAD = 0x4): Auto-Negotiation Advertisement Ability Bit Name R/W 15 Next page RO 14 Reserved RO 13 Remote fault RO 12-11 Reserved ...
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PHY1 Register 29 (PHYAD = 0x1, REGAD = 0x1D): LinkMD Control/Status PHY2 Register 29 (PHYAD = 0x2, REGAD = 0x1D): LinkMD Control/Status Bit Name R/W 15 Vct_enable R/W (SC) 14-13 Vct_result RO 12 Vct 10M Short RO 11-9 Reserved RO ...
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Register Map: Switch & PHY (8-bit registers) Global Registers Register (Decimal) Register (Hex) 0-1 0x00-0x01 2-15 0x02-0x0F Port Registers Register (Decimal) Register (Hex) 16-29 0x10-0x1D 30-31 0x1E-0x1F 32-45 0x20-0x2D 46-47 0x2E-0x2F 48-57 0x30-0x39 58-62 0x3A-0x3E 63 0x3F 64-95 0x40-0x5F Advanced ...
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Register 1 (0x01): Chip ID1 / Start Switch Bit Name R/W 7-4 Chip ID RO 3-1 Revision Start Switch RW Register 2 (0x02): Global Control 0 Bit Name R/W 7 New Back-off R/W Enable 6-4 Reserved R/W ...
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Register 3 (0x03): Global Control 1 Bit Name R/W 7 Pass All R/W Frames 6 Reserved R/W 5 IEEE 802.3x R/W Transmit Direction Flow Control Enable 4 IEEE 802.3x R/W Receive Direction Flow Control Enable 3 Frame Length R/W Field ...
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Register 4 (0x04): Global Control 2 (continued) Bit Name R/W 4 Flow Control R/W and Back Pressure Fair Mode 3 No Excessive R/W Collision Drop 2 Huge Packet R/W Support 1 Legal R/W Maximum Packet Size Check Enable 0 Priority ...
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Register 5 (0x05): Global Control 3 (continued) Bit Name R/W 3 Weighted R/W Fair Queue Enable 2-1 Reserved R/W 0 Sniff Mode R/W Select Register 6 (0x06): Global Control 4 Bit Name R/W 7 Repeater R/W Mode 6 Switch MII ...
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Register 6 (0x06): Global Control 4 (continued) Bit Name R/W 4 Switch MII R/W 10BT 3 Null VID R/W Replacement 2-0 Broadcast R/W Storm Protection (1) Rate Bit [10:8] Register 7 (0x07): Global Control 5 Bit Name R/W 7-0 Broadcast ...
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Register 11 (0x0B): Global Control 9 Bit Name R/W Description 7 LEDSEL1 R/W LED mode select See description in bit 1 of this register. 6-5 Reserved R/W Reserved Do not change the default values. 4 Reserved R/W Testing mode. Set ...
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Register 13 (0x0D): Global Control 11 Bit Name R/W Description 7-6 Tag_0x7 R/W IEEE 802.1p mapping. The value in this field is used as the frame’s priority when its IEEE 802.1p tag has a value of 0x7. 5-4 Tag_0x6 R/W ...
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Register 16 (0x10): Port 1 Control 0 Register 32 (0x20): Port 2 Control 0 Register 48 (0x30): Port 3 Control 0 Bit Name ...
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Register 17 (0x11): Port 1 Control 1 Register 33 (0x21): Port 2 Control 1 Register 49 (0x31): Port 3 Control 1 Bit Name R/W 7 Sniffer Port R/W 6 Receive Sniff R/W 5 Transmit Sniff R/W 4 Double Tag R/W ...
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Register 18 (0x12): Port 1 Control 2 Register 34 (0x22): Port 2 Control 2 Register 50 (0x32): Port 3 Control 2 Bit Name R/W 7 Reserved R/W 6 Ingress VLAN R/W Filtering 5 Discard non R/W PVID Packets 4 Force ...
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Register 19 (0x13): Port 1 Control 3 Register 35 (0x23): Port 2 Control 3 Register 51 (0x33): Port 3 Control 3 Bit Name R/W 7-0 Default Tag R/W [15:8] Register 20 (0x14): Port 1 Control 4 Register 36 (0x24): Port ...
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Register 22 (0x16): Port 1 Control 6 Register 38 (0x26): Port 2 Control 6 Register 54 (0x36): Port 3 Control 6 Bit Name R/W 7-4 Ingress Pri1 R/W Rate 3-0 Ingress Pri0 R/W Rate December 2007 Description Ingress data rate ...
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Register 23 (0x17): Port 1 Control 7 Register 39 (0x27): Port 2 Control 7 Register 55 (0x37): Port 3 Control 7 Bit Name R/W 7-4 Ingress Pri3 R/W Rate 3-0 Ingress Pri2 R/W Rate December 2007 Description Ingress data rate ...
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Register 24 (0x18): Port 1 Control 8 Register 40 (0x28): Port 2 Control 8 Register 56 (0x38): Port 3 Control 8 Bit Name R/W 7-4 Egress Pri1 R/W Rate 3-0 Egress Pri0 R/W Rate December 2007 Description Egress data rate ...
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Register 25 (0x19): Port 1 Control 9 Register 41 (0x29): Port 2 Control 9 Register 57 (0x39): Port 3 Control 9 Bit Name R/W 7-4 Egress Pri3 R/W Rate 3-0 Egress Pri2 R/W Rate December 2007 Description Egress data rate ...
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Note: Most of the contents in registers 26-31 and registers 42-47 for ports 1 and 2, respectively, can also be accessed with the MIIM PHY registers. Register 26 (0x1A): Port 1 PHY Special Control/Status Register 42 (0x2A): Port 2 PHY ...
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Register 28 (0x1C): Port 1 Control 12 Register 44 (0x2C): Port 2 Control 12 Register 60 (0x3C): Reserved, not applied to port 3 Bit Name R/W 7 Auto R/W Negotiation Enable 6 Force Speed R/W 5 Force Duplex R/W 4 ...
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Register 29 (0x1D): Port 1 Control 13 Register 45 (0x2D): Port 2 Control 13 Register 61 (0x3D): Reserved, not applied to port 3 Bit Name R/W 7 LED Off R/W 6 Txdis R/W 5 Restart AN R/W 4 Disable Far- ...
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Register 30 (0x1E): Port 1 Status 0 Register 46 (0x2E): Port 2 Status 0 Register 62 (0x3E): Reserved, not applied to port 3 Bit Name R/W MDI-X Status Done 6 RO Link Good 5 RO Partner Flow ...
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Register 31 (0x1F): Port 1 Status 1 (continued) Register 47 (0x2F): Port 2 Status 1 (continued) Register 63 (0x3F): Port 3 Status 1 (continued) Bit Name R/W 2 Operation RO Speed 1 Operation RO Duplex 0 Far-end Fault RO Advanced ...
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Register 97 (0x61): TOS Priority Control Register 1 Bit Name R/W 7-6 DSCP[15:14] R/W 5-4 DSCP[13:12] R/W 3-2 DSCP[11:10] R/W 1-0 DSCP[9:8] R/W Register 98 (0x62): TOS Priority Control Register 2 Bit Name R/W 7-6 DSCP[23:22] R/W 5-4 DSCP[21:20] R/W ...
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Register 99 (0x63): TOS Priority Control Register 3 Bit Name R/W 7-6 DSCP[31:30] R/W 5-4 DSCP[29:28] R/W 3-2 DSCP[27:26] R/W 1-0 DSCP[25:24] R/W Register 100 (0x64): TOS Priority Control Register 4 Bit Name R/W 7-6 DSCP[39:38] R/W 5-4 DSCP[37:36] R/W ...
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Register 101 (0x65): TOS Priority Control Register 5 Bit Name R/W 7-6 DSCP[47:46] R/W 5-4 DSCP[45:44] R/W 3-2 DSCP[43:42] R/W 1-0 DSCP[41:40] R/W Register 102 (0x66): TOS Priority Control Register 6 Bit Name R/W 7-6 DSCP[55:54] R/W 5-4 DSCP[53:52] R/W ...
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Register 103 (0x67): TOS Priority Control Register 7 Bit Name R/W 7-6 DSCP[63:62] R/W 5-4 DSCP[61:60] R/W 3-2 DSCP[59:58] R/W 1-0 DSCP[57:56] R/W Register 104 (0x68): TOS Priority Control Register 8 Bit Name R/W 7-6 DSCP[71:70] R/W 5-4 DSCP[69:68] R/W ...
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Register 105 (0x69): TOS Priority Control Register 9 Bit Name R/W 7-6 DSCP[79:78] R/W 5-4 DSCP[77:76] R/W 3-2 DSCP[75:74] R/W 1-0 DSCP[73:72] R/W Register 106 (0x6A): TOS Priority Control Register 10 Bit Name R/W 7-6 DSCP[87:86] R/W 5-4 DSCP[85:84] R/W ...
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Register 107 (0x6B): TOS Priority Control Register 11 Bit Name R/W 7-6 DSCP[95:94] R/W 5-4 DSCP[93:92] R/W 3-2 DSCP[91:90] R/W 1-0 DSCP[89:88] R/W Register 108 (0x6C): TOS Priority Control Register 12 Bit Name R/W 7-6 DSCP[103:102] R/W 5-4 DSCP[101:100] R/W ...
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Register 109 (0x6D): TOS Priority Control Register 13 Bit Name R/W 7-6 DSCP[111:110] R/W 5-4 DSCP[109:108] R/W 3-2 DSCP[107:106] R/W 1-0 DSCP[105:104] R/W Register 110 (0x6E): TOS Priority Control Register 14 Bit Name R/W 7-6 DSCP[119:118] R/W 5-4 DSCP[117:116] R/W ...
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Register 111 (0x6F): TOS Priority Control Register 15 Bit Name R/W 7-6 DSCP[127:126] R/W 5-4 DSCP[125:124] R/W 3-2 DSCP[123:122] R/W 1-0 DSCP[121:120] R/W Registers 112 to 117 Registers 112 to 117 contain the switch engine’s MAC address. This 48-bit address ...
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... Registers 118 to 120 Registers 118 to 120 are User Defined Registers (UDRs). These are general purpose read/write registers that can be used to pass user defined control and status information between the KSZ8893MQL/MBL and the external processor. Register 118 (0x76): User Defined Register 1 Bit ...
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Register 124 (0x7C): Indirect Data Register 7 Bit Name R/W 7-0 Indirect Data R/W [63:56] Register 125 (0x7D): Indirect Data Register 6 Bit Name R/W 7-0 Indirect Data R/W [55:48] Register 126 (0x7E): Indirect Data Register 5 Bit Name R/W ...
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Register 133 (0x85): Digital Testing Control 0 Bit Name R/W 7-0 Reserved R/W Register 134 (0x86): Analog Testing Control 0 Bit Name R/W 7-0 Reserved R/W Register 135 (0x87): Analog Testing Control 1 Bit Name R/W 7-0 Reserved R/W Register ...
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... Static MAC Address Table The KSZ8893MQL/MBL supports both a static and a dynamic MAC address table. In response to a Destination Address (DA) look up, the KSZ8893MQL/MBL searches both tables to make a packet forwarding decision. In response to a Source Address (SA) look up, only the dynamic table is searched for aging, migration and learning purposes ...
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... VID If 802.1Q VLAN mode is enabled, KSZ8893MQL/MBL will assign a VID to every ingress packet. If the packet is untagged or tagged with a null VID, the packet is assigned with the default port VID of the ingress port. If the packet is tagged with non null VID, the VID in the tag will be used. The look up process will start from the VLAN table look up ...
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... Write to reg. 130 (0x82), VLAN table bits [15:8] Write to reg. 131 (0x83), VLAN table bits [7:0] Write to reg. 121 (0x79) with 0x04 Write to reg. 122 (0x7A) with 0x06 Dynamic MAC Address Table The KSZ8893MQL/MBL maintains the dynamic MAC address table. Read access is allowed only. Bit Name 71 Data Not ...
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... MIB (Management Information Base) Counters The KSZ8893MQL/MBL provides 34 MIB counters per port. These counters are used to monitor the port activity for network management. The MIB counters have two format groups: “Per Port” and “All Port Dropped Packet.” Bit Name ...
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Offset Counter Name 0x13 Rx1024to1522Octets 0x14 TxLoPriorityByte 0x15 TxHiPriorityByte 0x16 TxLateCollision 0x17 TxPausePkts 0x18 TxBroadcastPkts 0x19 TxMulticastPkts 0x1A TxUnicastPkts 0x1B TxDeferred 0x1C TxTotalCollision 0x1D TxExcessiveCollision 0x1E TxSingleCollision 0x1F TxMultipleCollision Table 20. Port 1’s “Per Port” MIB Counters Indirect Memory Offsets ...
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Read reg. 128 (0x80), overflow bit [31] Read reg. 129 (0x81), counter bits [23:16] Read reg. 130 (0x82), counter bits [15:8] Read reg. 131 (0x83), counter bits [7:0] 2. MIB Counter Read (Read port 2 “Rx64Octets” Counter) Write to reg. ...
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Absolute Maximum Ratings Supply Voltage ( ........................... –0.5V to +4.0V DDATX DDARX DDIO Input Voltage (all inputs). ............................. –0.5V to +5.0V Output Voltage (all outputs) ......................... –0.5V to +4.0V Lead Temperature (soldering, 10sec.) ....................... 270°C ...
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... Electrical Characteristics Parameter - Current consumption is for the single 3.3V supply KSZ8893MQL/MBL device only, and includes the 1.2V Supply Current supply voltages (VDDA, VDDAP, VDDC) that are provided by the KSZ8893MQL/MBL via power output pin 22. - Each PHY port’s transformer consumes an additional 45mA @ 3.3V for 100BASE-TX and 70mA @ 3.3V for 10BASE-T ...
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Notes: 1. Exceeding the absolute maximum rating may damage the device. Stresses greater than those listed in the table above may cause permanent damage to the device. Operation of the device at these or any other conditions above those specified ...
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Timing Specifications EEPROM Timing Figure 14. EEPROM Interface Input Timing Diagram Figure 15. EEPROM Interface Output Timing Diagram Timing Parameter Description Clock cycle t cyc1 Setup time t s1 Hold time t h1 Output valid t ov1 December 2007 Min ...
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SNI Timing Timing Parameter Description Clock cycle t cyc2 Setup time t s2 Hold time t h2 Output valid t ov2 December 2007 Figure 16. SNI Input Timing Diagram Figure 17. SNI Output Timing Diagram Min Typ 100 10 0 ...
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MII Timing MAC Mode MII Timing Figure ...
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PHY Mode MII Timing Figure 20. PHY Mode MII Timing – Data Received from MII Figure 21. PHY Mode MII Timing – Data Transmitted to MII Timing Parameter Description tcyc4 Clock cycle (100BASE-TX) 100BASE-TX tcyc4 Clock cycle 10BASE-T (10BASE-T) ts4 ...
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RMII Timing Receive Tim ing ...
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I2C Slave Mode Timing Timing Parameter Tcyc Ts Th Ttbs Ttbh Tsbs Tsbh Tov Note: Data is only allowed to change during SCL low time except start and stop bits. December 2007 Figure 24. I2C Input Timing Figure 25. I2C ...
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SPI Timing Input Timing Timing Parameter fC tCHSL tSLCH tCHSH tSHCH tSHSL tDVCH tCHDX tCLCH tCHCL tDLDH tDHDL December 2007 Figure 28. SPI Input Timing Description Clock frequency SPIS_N inactive hold time SPIS_N active setup time SPIS_N active old time ...
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Output Timing Timing Parameter fC tCLQX tCLQV tCH tCL tQLQH tQHQL tSHQZ December 2007 Figure 29. SPI Output Timing Description Clock frequency SPIQ hold time Clock low to SPIQ valid Clock high time Clock low time SPIQ rise time SPIQ ...
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Auto-Negotiation Timing A u to-N egotiation - F ast ulse T im ing Timing Parameter Description t FLP burst to FLP burst BTB t ...
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... Reset Timing The KSZ8893MQL/MBL reset timing requirement is summarized in the following figure and table. Parameter Stable supply voltages to reset High t sr Configuration setup time Configuration hold time ch Reset to strap-in pin output t rc After the de-assertion of reset recommended to wait a minimum of 100 us before starting programming on the managed interface (I2C slave, SPI slave, SMI, MIIM) ...
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... Reset Circuit The reset circuit in Figure 32 is recommended for powering up the KSZ8893MQL/MBL if reset is triggered only by the power supply. KS8893M The reset circuit in Figure 33 is recommended for applications where reset is driven by another device (e.g., CPU, FPGA, etc),. At power-on-reset and D1 provide the necessary ramp rise time to reset the KSZ8893MQL/MBL device ...
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Selection of Isolation Transformers An 1:1 isolation transformer is required at the line interface. An isolation transformer with integrated common- mode choke is recommended for exceeding FCC requirements. The following table gives recommended transformer characteristics. Parameter Turns ratio Open-circuit inductance ...
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Package Information December 2007 Figure 34. 128-Pin PQFP Package 114 M9999-121007-1.5 ...
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December 2007 Figure 35. 100_Ball LFBGA Package 115 M9999-121007-1.5 ...
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MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA TEL: +1 (408) 944-0800 The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. ...