EVAL-AD1938AZ Analog Devices Inc, EVAL-AD1938AZ Datasheet - Page 9

• Manufacturer Part Number: EVAL-AD1938AZ
• Description: Eval BD FOR MULTI CHANNEL 96KHz Codec
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1938AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1938
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 108dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
Table 10. Pin Function Descriptions
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
In/Out
I
I
O
I
I
O
O
O
O
I
I/O
I
I
I/O
I/O
I
I/O
I/O
I/O
O
I/O
I/O
I
I/O
I
I
I
O
Mnemonic
AGND
MCLKI/XI
MCLKO/XO
AGND
AVDD
OL3
OR3
OL4
OR4
PD/RST
DSDATA4
DGND
DVDD
DSDATA3
DSDATA2
DSDATA1
DBCLK
DLRCLK
ASDATA2
ASDATA1
ABCLK
ALRCLK
CIN
COUT
DGND
CCLK
CLATCH
OL1
MCLKO/XO
DSDATA4
MCLKI/XI
PD/RST
AGND
AGND
DGND
AVDD
Description
Analog Ground.
Master Clock Input/Crystal Oscillator Input.
Master Clock Output/Crystal Oscillator Output.
Analog Ground.
Analog Power Supply. Connect to analog 3.3 V supply.
DAC 3 Left Output.
DAC 3 Right Output.
DAC 4 Left Output.
DAC 4 Right Output.
Power-Down Reset (Active Low).
DAC Input 4. Input to DAC L4 and DAC R4/DAC TDM Data Out 2/AUX ADC 1 Data In.
Digital Ground.
Digital Power Supply. Connect to digital 3.3 V supply.
DAC Input 3. Input to DAC L3 and DAC R3/DAC TDM Data In 2/Aux DAC 2 Data Out.
DAC Input 2. Input to DAC L2 and DAC R2/DAC TDM Data Out/AUX ADC 1 Data In.
DAC Input 1. Input to DAC L1 and DAC R1/DAC TDM Data In/AUX ADC 2 Data In.
Bit Clock for DACs.
LR Clock for DACs.
ADC Serial Data Output 2 (ADC L2 and ADC R2)/ADC TDM Data Input/Aux DAC 1 Data Out.
ADC Serial Data Output 1 (ADC L1 and ADC R1)/ADC TDM Data Output.
Bit Clock for ADCs.
LR Clock for ADCs.
Control Data Input (SPI).
Control Data Output (SPI).
Digital Ground.
Control Clock Input (SPI).
Latch Input for Control Data (SPI).
DAC 1 Left Output.
OR3
OR4
OL3
OL4
10
11
12
1
2
3
4
5
6
7
8
9
48
13
Figure 2. Pin Configuration, 48-Lead LQFP
47
14
46
15
45
16
Rev. C | Page 9 of 32
SINGLE-ENDED
44
17
(Not to Scale)
AD1938
TOP VIEW
OUTPUT
43
18
42
19
41
20
40
21
39
22
38
23
37
24
36
35
34
33
32
31
30
29
28
27
26
25
AGND
FILTR
AGND
AVDD
AGND
OR2
OL2
OR1
OL1
CLATCH
CCLK
DGND
AD1938