EVAL-AD1938AZ Analog Devices Inc, EVAL-AD1938AZ Datasheet - Page 25

• Manufacturer Part Number: EVAL-AD1938AZ
• Description: Eval BD FOR MULTI CHANNEL 96KHz Codec
• Manufacturer: Analog Devices Inc

Specifications of EVAL-AD1938AZ

• Main Purpose: Audio, CODEC
• Utilized Ic / Part: AD1938
• Primary Attributes: 24-Bit, 192 kHz, 4 ADCs: 107dB Dynamic Range, 8 DACs: 108dB Dynamic Range
• Secondary Attributes: Time Division Multiplexed (TDM), SPI Interface
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Embedded: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 17. PLL and Clock Control Register 1
Bit
0
1
2
3
7:4
DAC CONTROL REGISTERS
Table 18. DAC Control Register 0
Bit
0
2:1
5:3
7:6
Table 19. DAC Control Register 1
Bit
0
2:1
3
4
5
6
7
Value
0
1
0
1
0
1
0
1
0000
Value
0
1
00
01
10
11
000
001
010
011
100
101
110
111
00
01
10
11
Value
0
1
00
01
10
11
0
1
0
1
0
1
0
1
0
1
Function
Normal
Power-down
32 kHz/44.1 kHz/48 kHz
64 kHz/88.2 kHz/96 kHz
128 kHz/176.4 kHz/192 kHz
Reserved
1
0
8
12
16
Reserved
Reserved
Reserved
Stereo (normal)
TDM (daisy chain)
DAC AUX mode (ADC-, DAC-, TDM-coupled)
Dual-line TDM
Function
Latch in mid cycle (normal)
Latch in at end of cycle (pipeline)
64 (2 channels)
128 (4 channels)
256 (8 channels)
512 (16 channels)
Left low
Left high
Slave
Master
Slave
Master
DBCLK pin
Internally generated
Normal
Inverted
Function
PLL clock
MCLK
PLL clock
MCLK
Enabled
Disabled
Not locked
Locked
Reserved
Rev. C | Page 25 of 32
Description
DAC clock source select
ADC clock source select
On-chip voltage reference
PLL lock indicator (read-only)
Description
Power-down
Sample rate
SDATA delay (BCLK periods)
Serial format
Description
BCLK active edge (TDM in)
BCLKs per frame
LRCLK polarity
LRCLK master/slave
BCLK master/slave
BCLK source
BCLK polarity
AD1938