EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 125
EP2SGX90EF1152I4N
Manufacturer Part Number
EP2SGX90EF1152I4N
Description
Stratix II GX
Manufacturer
Altera
Datasheet
1.EP2SGX90EF1152I4N.pdf
(316 pages)
Specifications of EP2SGX90EF1152I4N
Family Name
Stratix II GX
Number Of Logic Blocks/elements
90960
# I/os (max)
558
Frequency (max)
732.1MHz
Process Technology
SRAM
Operating Supply Voltage (typ)
1.2V
Logic Cells
90960
Ram Bits
4520448
Operating Supply Voltage (min)
1.15V
Operating Supply Voltage (max)
1.25V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
1152
Package Type
FC-FBGA
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
EP2SGX90EF1152I4N
Manufacturer:
ALTERA
Quantity:
535
Part Number:
EP2SGX90EF1152I4N
Manufacturer:
ALTERA/阿尔特拉
Quantity:
20 000
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Figure 2–81. Stratix II GX IOE in Bidirectional I/O Configuration
Notes to
(1)
(2)
Altera Corporation
October 2007
Column, Row,
Interconnect
or Local
All input signals to the IOE can be inverted at the IOE.
The optional PCI clamp is only available on column I/O pins.
ioe_clk[7..0]
Figure
2–81:
clkout
clkin
oe
ce_out
aclr/apreset
ce_in
sclr/spreset
Chip-Wide Reset
The Stratix II GX device IOE includes programmable delays that can be
activated to ensure input IOE register-to-logic array register transfers,
input pin-to-logic array register transfers, or output IOE register-to-pin
transfers.
Output Register
Input Register
OE Register
D
CLRN/PRN
ENA
ENA
D
CLRN/PRN
D
CLRN/PRN
ENA
Q
Q
Q
Drive Strength Control
Open-Drain Output
Pin Delay
Output
Input Register Delay
Logic Array Delay
Stratix II GX Device Handbook, Volume 1
Input Pin to
Input Pin to
Note (1)
OE Register
t
CO
Delay
V
Stratix II GX Architecture
CCIO
PCI Clamp (2)
V
CCIO
Bus-Hold
Termination
Circuit
On-Chip
Programmable
Pull-Up
Resistor
2–117
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