EP2SGX90EF1152I4N Altera, EP2SGX90EF1152I4N Datasheet - Page 11

• Manufacturer Part Number: EP2SGX90EF1152I4N
• Description: Stratix II GX
• Manufacturer: Altera

Specifications of EP2SGX90EF1152I4N

• Family Name: Stratix II GX
• Number Of Logic Blocks/elements: 90960
• # I/os (max): 558
• Frequency (max): 732.1MHz
• Process Technology: SRAM
• Operating Supply Voltage (typ): 1.2V
• Logic Cells: 90960
• Ram Bits: 4520448
• Operating Supply Voltage (min): 1.15V
• Operating Supply Voltage (max): 1.25V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 1152
• Package Type: FC-FBGA
• Lead Free Status / Rohs Status: Compliant

Altera Corporation
October 2007
Figure 2–2. Elements of the Transceiver Block
Each Stratix II GX transceiver channel consists of a transmitter and
receiver. The transceivers are grouped in four and share PLL resources.
Each transmitter has access to one of two PLLs. The transmitter contains
the following:
■
■
■
■
■
The receiver contains the following:
■
■
■
■
■
■
■
■
■
■
■
■
Designers can preset Stratix II GX transceiver functions using the
Quartus
differential output voltage (V
Stratix II GX transceiver channel supports various loopback modes and is
Transmitter phase compensation first-in first-out (FIFO) buffer
Byte serializer (optional)
8B/10B encoder (optional)
Serializer (parallel-to-serial converter)
Transmitter differential output buffer
Receiver differential input buffer
Receiver lock detector and run length checker
Clock recovery unit (CRU)
Deserializer
Pattern detector
Word aligner
Lane deskew
Rate matcher (optional)
8B/10B decoder (optional)
Byte deserializer (optional)
Byte ordering
Receiver phase compensation FIFO buffer
®
II software. In addition, pre-emphasis, equalization, and
Stratix II GX
Logic Array
Transceiver Block
(PLLs, State Machines,
OD
Supporting Blocks
Programming)
) are dynamically programmable. Each
Channel 1
Channel 0
Channel 2
Channel 3
Stratix II GX Device Handbook, Volume 1
Stratix II GX Architecture
RX1
TX1
RX0
TX0
REFCLK_1
REFCLK_0
RX2
TX2
RX3
TX3
2–3