DSPIC33FJ16GP304T-I/ML Microchip Technology, DSPIC33FJ16GP304T-I/ML Datasheet - Page 58
![16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R](/photos/6/81/68122/150-44-qfn_sml.jpg)
DSPIC33FJ16GP304T-I/ML
Manufacturer Part Number
DSPIC33FJ16GP304T-I/ML
Description
16-bit DSC, 16KB Flash,40 MIPS,nanoWatt 44 QFN 8x8x0.9mm T/R
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr
Datasheets
1.DSPIC33FJ12MC201-ISO.pdf
(14 pages)
2.DSPIC33FJ16GP304-IPT.pdf
(284 pages)
3.DSPIC33FJ16GP304-IPT.pdf
(8 pages)
4.DSPIC33FJ16GP304-IPT.pdf
(14 pages)
Specifications of DSPIC33FJ16GP304T-I/ML
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
35
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 13x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
44-QFN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DSPIC33FJ16GP304T-I/MLTR
- DSPIC33FJ12MC201-ISO PDF datasheet
- DSPIC33FJ16GP304-IPT PDF datasheet #2
- DSPIC33FJ16GP304-IPT PDF datasheet #3
- DSPIC33FJ16GP304-IPT PDF datasheet #4
- Current page: 58 of 284
- Download datasheet (4Mb)
dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
5.2
The
dsPIC33FJ16GP304 Flash program memory array is
organized into rows of 64 instructions or 192 bytes.
RTSP allows the user application to erase a page of
memory, which consists of eight rows (512 instructions)
at a time, and to program one row or one word at a
time. The 8-row erase pages and single row write rows
are edge-aligned from the beginning of program
memory, on boundaries of 1536 bytes and 192 bytes,
respectively.
The program memory implements holding buffers that
can contain 64 instructions of programming data. Prior
to the actual programming operation, the write data
must be loaded into the buffers sequentially. The
instruction words loaded must always be from a group
of 64 boundary.
The basic sequence for RTSP programming is to set up
a Table Pointer, then do a series of TBLWT instructions
to load the buffers. Programming is performed by
setting the control bits in the NVMCON register. A total
of 64 TBLWTL and TBLWTH instructions are required
to load the instructions.
All of the table write operations are single-word writes
(two instruction cycles) because only the buffers are
written.
programming each row.
5.3
A complete programming sequence is necessary for
programming or erasing the internal Flash in RTSP
mode.
programming operation is finished.
The programming time depends on the FRC accuracy
(see
Tuning register (see
formula to calculate the minimum and maximum values
for the Row Write Time, Page Erase Time, and Word
Write Cycle Time parameters (see
EQUATION 5-1:
DS70290G-page 58
------------------------------------------------------------------------------------------------------------------------- -
7.37 MHz
Table
The
RTSP Operation
Programming Operations
A
22-18) and the value of the FRC Oscillator
programming
×
dsPIC33FJ32GP202/204
processor
(
FRC Accuracy
Register
PROGRAMMING TIME
T
stalls
cycle
)%
8-4). Use the following
×
Table
(
(waits)
FRC Tuning
is
22-12).
required
until
)%
and
the
for
For example, if the device is operating at +125°C, the
FRC accuracy will be ±5%. If the TUN<5:0> bits (see
Register
write time is equal to
EQUATION 5-2:
The maximum row write time is equal to
EQUATION 5-3:
Setting the WR bit (NVMCON<15>) starts the
operation, and the WR bit is automatically cleared
when the operation is finished.
5.4
The two SFRs that are used to read and write the
program Flash memory are:
•
•
The NVMCON register
blocks are to be erased, which memory type is to be
programmed and the start of the programming cycle.
NVMKEY
used for write protection. To start a programming or
erase
consecutively write 0x55 and 0xAA to the NVMKEY
register.
Operations”
T
T
RW
RW
NVMCON: Flash Memory Control Register
NVMKEY: Nonvolatile Memory Key Register
=
=
--------------------------------------------------------------------------------------------- - 1.586ms
7.37 MHz
---------------------------------------------------------------------------------------------- 1.435ms
7.37 MHz
sequence,
8-4) are set to ‘b111111, the minimum row
Control Registers
(Register
Refer
for further details.
×
×
(
to
(
11064 Cycles
11064 Cycles
5-2) is a write-only register that is
1 0.05
1
Equation
–
+
the
MINIMUM ROW WRITE
TIME
MAXIMUM ROW WRITE
TIME
© 2011 Microchip Technology Inc.
0.05
Section 5.3
(Register
)
)
user
×
×
5-2.
(
(
1 0.00375
1 0.00375
–
–
5-1) controls which
application
“Programming
Equation
)
)
=
=
must
5-3.
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