DSPIC33EP256MU810-E/PF Microchip Technology, DSPIC33EP256MU810-E/PF Datasheet - Page 450

• Manufacturer Part Number: DSPIC33EP256MU810-E/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
TABLE 30-2:
DS70616E-page 450
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
Note
Base
Instr
#
Mnemonic
DAW
DEC
DEC2
DISI
DIV
DIVF
DO
ED
EDAC
EXCH
FBCL
FF1L
FF1R
GOTO
INC
INC2
IOR
LAC
LNK
LSR
MAC
Assembly
1:
2:
This instruction is available in dsPIC33EPXXXMU806/810/814 devices only.
Read and Read-Modify-Write (e.g., bit operations and logical operations) on non-CPU SFRs incur an additional instruction cycle.
DAW
DEC
DEC
DEC
DEC2
DEC2
DEC2
DISI
DIV.S
DIV.SD
DIV.U
DIV.UD
DIVF
DO
DO
ED
EDAC
EXCH
FBCL
FF1L
FF1R
GOTO
GOTO
GOTO.L
INC
INC
INC
INC2
INC2
INC2
IOR
IOR
IOR
IOR
IOR
LAC
LNK
LSR
LSR
LSR
LSR
LSR
MAC
MAC
INSTRUCTION SET OVERVIEW (CONTINUED)
Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
#lit14
Wm,Wn
Wm,Wn
Wm,Wn
Wm,Wn
#lit15,Expr
Wn,Expr
Wm*Wm,Acc,Wx,Wy,Wxd
Wm*Wm,Acc,Wx,Wy,Wxd
Wns,Wnd
Ws,Wnd
Ws,Wnd
Ws,Wnd
Expr
Wn
Wn
f
f,WREG
Ws,Wd
f
f,WREG
Ws,Wd
f
f,WREG
#lit10,Wn
Wb,Ws,Wd
Wb,#lit5,Wd
Wso,#Slit4,Acc
#lit14
f
f,WREG
Ws,Wd
Wb,Wns,Wnd
Wb,#lit5,Wnd
Wm*Wn,Acc,Wx,Wxd,Wy,Wyd,AWB
Wm*Wm,Acc,Wx,Wxd,Wy,Wyd
Wm,Wn
Assembly Syntax
(1)
(1)
(1)
(1)
(1)
(1)
Preliminary
(1)
Wn = decimal adjust Wn
f = f – 1
WREG = f – 1
Wd = Ws – 1
f = f – 2
WREG = f – 2
Wd = Ws – 2
Disable Interrupts for k instruction cycles
Signed 16/16-bit Integer Divide
Signed 32/16-bit Integer Divide
Unsigned 16/16-bit Integer Divide
Unsigned 32/16-bit Integer Divide
Signed 16/16-bit Fractional Divide
Do code to PC + Expr, lit15 + 1 times
Do code to PC + Expr, (Wn) + 1 times
Euclidean Distance (no accumulate)
Euclidean Distance
Swap Wns with Wnd
Find Bit Change from Left (MSb) Side
Find First One from Left (MSb) Side
Find First One from Right (LSb) Side
Go to address
Go to indirect
Go to indirect (long address)
f = f + 1
WREG = f + 1
Wd = Ws + 1
f = f + 2
WREG = f + 2
Wd = Ws + 2
f = f .IOR. WREG
WREG = f .IOR. WREG
Wd = lit10 .IOR. Wd
Wd = Wb .IOR. Ws
Wd = Wb .IOR. lit5
Load Accumulator
Link Frame Pointer
f = Logical Right Shift f
WREG = Logical Right Shift f
Wd = Logical Right Shift Ws
Wnd = Logical Right Shift Wb by Wns
Wnd = Logical Right Shift Wb by lit5
Multiply and Accumulate
Square and Accumulate
Description
 2009-2011 Microchip Technology Inc.
Words
# of
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Cycles
# of
18
18
18
18
18
1
1
1
1
1
1
1
1
2
2
1
1
1
1
1
1
4
4
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
(2)
Status Flags
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,OAB,
OA,OB,OAB,
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
C,DC,N,OV,Z
OA,OB,OAB,
OA,OB,OAB,
OA,OB,OAB,
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
SA,SB,SAB
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
N,Z,C,OV
C,N,OV,Z
C,N,OV,Z
C,N,OV,Z
Affected
None
None
None
None
None
None
None
SFA
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
N,Z
C
C
C
C