DSPIC33EP256MU810-E/PF Microchip Technology, DSPIC33EP256MU810-E/PF Datasheet - Page 112

• Manufacturer Part Number: DSPIC33EP256MU810-E/PF
• Description: 100 PINS, 256KB Flash, 28KB RAM, 60 MHz, USB, 2xCAN, 15 DMA 100 TQFP 14x14x1mm T
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33EPr

Specifications of DSPIC33EP256MU810-E/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 60 MIPs
• Connectivity: CAN, I²C, IrDA, LIN, QEI, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, DMA, Motor Control PWM, POR, PWM, WDT
• Number Of I /o: 83
• Program Memory Size: 256KB (85.5K x 24)
• Program Memory Type: FLASH
• Eeprom Size: -
• Ram Size: 12K x 16
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 32x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 100-TQFP
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33EPXXXMU806/810/814 and PIC24EPXXXGU810/814
4.2.7
The
PIC24EPXXXGU810/814 architecture extends the
available data space through a paging scheme, which
allows the available data space to be accessed using
MOV instructions in a linear fashion for pre- and post-
modified effective addresses (EA). The upper half of
base data space address is used in conjunction with
the data space page registers, the 10-bit read page
register (DSRPAG) or the 9-bit write page register
(DSWPAG), to form an extended data space (EDS)
address or Program Space Visibility (PSV) address.
The data space page registers are located in the SFR
space.
EXAMPLE 4-1:
DS70616E-page 112
Note: DS read access when DSRPAG = 0x000 will force an Address Error trap.
dsPIC33EPXXXMU806/810/814
PAGED MEMORY SCHEME
(DSRPAG = don't care)
EXTENDED DATA SPACE (EDS) READ ADDRESS GENERATION
EA<15> = 0
PSV address
Generate
0
DSRPAG
DSRPAG<8:0>
No EDS access
Select
Y
and
Preliminary
DSRPAG<9>
DSRPAG<9>
9 bits
N
= 1?
24-bit EDS EA
Construction of the EDS address is shown in
When DSRPAG<9> = 0 and base address bit
EA<15> = 1, DSRPAG<8:0> is concatenated onto
EA<14:0> to form the 24-bit EDS read address. Similarly
when base address bit EA<15>=1, DSWPAG<8:0> is
concatenated onto EA<14:0> to form the 24-bit EDS
write address.
EA<15>
1
0
16-bit DS EA
15 bits
EA
EA
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Select
Byte
Select
Byte
Figure
4-1.