CYV15G0204TRB-BGXC Cypress Semiconductor Corp, CYV15G0204TRB-BGXC Datasheet - Page 14

• Manufacturer Part Number: CYV15G0204TRB-BGXC
• Description: IC,TV/VIDEO CIRCUIT,Data Serializer,BICMOS,BGA,256PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp

Specifications of CYV15G0204TRB-BGXC

• Function: Serializer/Deserializer
• Data Rate: 1.485Gbps
• Input Type: LVTTL
• Output Type: PECL
• Number Of Inputs: 4
• Number Of Outputs: 4
• Voltage - Supply: 3.15 V ~ 3.45 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 256-LBGA Exposed Pad, 32-HLBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Document Number : 38-02101 Rev. *D
Table 2. Analog Amplitude Detect Valid Signal Levels
Transition Density
The Transition Detection logic checks for the absence of
transitions spanning greater than six transmission characters
(60 bits). If no transitions are present in the data received, the
Detection logic for that channel asserts LFIx.
Range Controls
The CDR circuit includes logic to monitor the frequency of the
PLL Voltage Controlled Oscillator (VCO) used to sample the
incoming data stream. This logic ensures that the VCO
operates at, or near the rate of the incoming data stream for
two primary cases:
To perform this function, the frequency of the RXPLL VCO is
periodically compared to the frequency of the TRGCLKx±
input. If the VCO is running at a frequency beyond
±1500 ppm
periodically forced to the correct frequency (as defined by
TRGCLKx±, SPDSELx, and TRGRATEx) and then released in
an attempt to lock to the input data stream.
The sampling and relock period of the Range Control is calcu-
lated as follows: RANGE_CONTROL_ SAMPLING_PERIOD
= (RECOVERED BYTE CLOCK PERIOD) * (4096).
During the time that the Range Control forces the RXPLL VCO
to track TRGCLKx±, the LFIx output is asserted LOW. After a
valid serial data stream is applied, it may take up to one
RANGE CONTROL SAMPLING PERIOD before the PLL
locks to the input data stream, after which LFIx should be
HIGH.
The operating serial signaling-rate and allowable range of
TRGCLK± frequencies are listed in
Table 3. Operating Speed Settings
Note
SDASEL Typical Signal with Peak Amplitudes Above
7. The peak amplitudes listed in this table are for typical waveforms that have generally 3–4 transitions for every ten bits. In a worse case environment the signals
• when the incoming data stream resumes after a time in
• when the incoming data stream is outside the acceptable
MID (Open)
SPDSELx
which it has been “missing.”
signaling rate range.
may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase
the values in the table above by approximately 100 mV.
00
01
10
11
HIGH
LOW
Analog Signal Detector is disabled
140 mV p-p differential
280 mV p-p differential
420 mV p-p differential
[23]
as defined by the TRGCLKx± frequency, it is
TRGRATEx
1
0
1
0
1
0
TRGCLKx±
Frequency
reserved
19.5–40
80–150
20–40
40–75
(MHz)
40–80
Table
3.
Rate (Mbps)
Signaling
195 – 400
800–1500
400–800
[7]
Receive Channel Enabled
The CYV15G0204TRB contains two receive channels that can
be independently enabled and disabled. Each channel can be
enabled or disabled separately through the RXPLLPDx input
latch as controlled by the device configuration interface. When
the RXPLLPDx latch = 0, the associated PLL and analog
circuitry of the channel is disabled. Any disabled channel
indicates a constant link fault condition on the LFIx output.
When RXPLLPDx = 1, the associated PLL and receive
channel is enabled to receive a serial stream.
When a disabled receive channel is reenabled, the status of
the associated LFIx output and data on the parallel outputs for
the associated channel may be indeterminate for up to 2 ms.
Clock/Data Recovery
The extraction of a bit-rate clock and recovery of bits from each
received serial stream is performed by a separate CDR block
within each receive channel. The clock extraction function is
performed by an integrated PLL that tracks the frequency of
the transitions in the incoming bit stream and align the phase
of the internal bit-rate clock to the transitions in the selected
serial data stream.
Each CDR accepts a character-rate (bit-rate
half-character-rate (bit-rate
associated TRGCLKx± input. This TRGCLKx± input is used to
Regardless of the type of signal present, the CDR attempts to
recover a data stream from it. If the signalling rate of the
recovered data stream is outside the limits set by the range
control monitors, the CDR tracks TRGCLKx± instead of the
data stream. Once the CDR output (RXCLK±) frequency
returns back close to TRGCLKx± frequency, the CDR input is
switched back to the input data stream. If no data is present at
the selected line receiver, this switching behavior may result
in brief RXCLK± frequency excursions from TRGCLKx±.
However, the validity of the input data stream is indicated by
the LFIx output. The frequency of TRGCLKx± is required to be
within ±1500ppm
the REFCLKx± input of the remote transmitter to ensure a lock
to the incoming data stream. This large ppm tolerance allows
the CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps
SMPTE HD-SDI data stream with a constant TRGCLK
frequency.
For systems using multiple or redundant connections, the LFIx
output can be used to select an alternate data stream. When
an LFIx indication is detected, external logic can toggle
selection of the associated INx1± and INx2± input through the
associated INSELx input. When a port switch takes place, it is
necessary for the receive PLL for that channel to reacquire the
new serial stream.
• ensure that the VCO (within the CDR) is operating at the
• reduce PLL acquisition time
• limit unlocked frequency excursions of the CDR VCO when
correct frequency (rather than a harmonic of the bit-rate)
there is no input data present at the selected Serial Line
Receiver.
[23]
of the frequency of the clock that drives
÷
CYV15G0204TRB
20) training clock from the
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