CY8CTST200A-16LGXI Cypress Semiconductor Corp, CY8CTST200A-16LGXI Datasheet - Page 77
CY8CTST200A-16LGXI
Manufacturer Part Number
CY8CTST200A-16LGXI
Description
CY8CTST200A-16LGXI
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-16LGXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
13
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.3
The following registers are associated with Sleep and Watchdog operations and are listed in address order. Each register
description has an associated register table showing the bit structure for that register. The bits that are grayed out in the
tables below are reserved bits and are not detailed in the register descriptions. Always write reserved bits with a value of ‘0’.
For a complete table of the Sleep and Watchdog registers, refer to the
10.3.1
The Reset Watchdog Timer Register (RES_WDT) clears the
watchdog timer (a write of any value) and clears both the
watchdog timer and the sleep timer (a write of 38h).
Bits 7 to 0: WDSL_Clear[7:0]. The
(WDT) write-only register is designed to timeout at three
sleep timer rollover events. If only the WDT is cleared, the
next Watchdog Reset (WDR) occurs anywhere from two to
three times the current sleep interval setting. If the sleep
timer is near the beginning of its count, the watchdog time-
out is closer to three times.
10.3.2
The Sleep Configuration Register (SLP_CFG) sets the sleep
duty cycle.
The value placed in this register is based upon factory test-
ing.
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
0,E3h
1,EBh
Address
Address
Register Definitions
RES_WDT
SLP_CFG
RES_WDT Register
SLP_CFG Register
Name
Name
Bit 7
Bit 7
PSSDC[1:0]
Bit 6
Bit 6
Watchdog
Bit 5
Bit 5
Timer
Bit 4
Bit 4
WDSL_Clear[7:0]
However, if the sleep timer is very close to its terminal
count, the watchdog timeout is closer to two times. To
ensure a full three times timeout, clear both the WDT and
the sleep timer. In applications that need a realtime clock
and cannot reset the sleep timer when clearing the WDT, the
duty cycle at which the WDT must be cleared is no greater
than two times the sleep interval.
For additional information, refer to the
on page
Bits 7 and 6: PSSDC[1:0]. The Power System Sleep Duty
Cycle bits set the sleep duty cycle.
For additional information, refer to the
page
283.
Summary Table of the Core Registers on page
Bit 3
Bit 3
253.
Bit 2
Bit 2
Bit 1
Bit 1
SLP_CFG register on
Sleep and Watchdog
RES_WDT register
Bit 0
Bit 0
Access
Access
RW : 0
W : 00
24.
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