CY8CTST200A-16LGXI Cypress Semiconductor Corp, CY8CTST200A-16LGXI Datasheet - Page 10
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CY8CTST200A-16LGXI
Manufacturer Part Number
CY8CTST200A-16LGXI
Description
CY8CTST200A-16LGXI
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200A-16LGXI
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
13
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
*
Package / Case
*
Processor Series
CY8CTxx2xxA
Core
M8C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Contents
10
19. Programmable Timer
20. Full-Speed USB
18.2 Register Definitions ..............................................................................................................147
18.3 Timing Diagrams ..................................................................................................................151
19.1 Architectural Description.......................................................................................................161
19.2 Register Definitions ..............................................................................................................163
20.1 Architectural Description.......................................................................................................165
20.2 Application Description .........................................................................................................165
20.3 Register Definitions ..............................................................................................................171
18.2.1 SPI_TXR Register ...................................................................................................147
18.2.2 SPI_RXR Register...................................................................................................148
18.2.3 SPI_CR Register .....................................................................................................149
18.2.4 SPI_CFG Register...................................................................................................150
18.2.5 Related Registers ....................................................................................................150
18.3.1 SPI Mode Timing .....................................................................................................151
18.3.2 SPIM Timing ............................................................................................................152
18.3.3 SPIS Timing.............................................................................................................157
19.1.1 Operation.................................................................................................................161
19.2.1 PT0_CFG Register ..................................................................................................163
19.2.2 PT1_CFG Register ..................................................................................................163
19.2.3 PT2_CFG Register ..................................................................................................164
19.2.4 PTx_DATA0 Register...............................................................................................164
19.2.5 PTx_DATA1 Register...............................................................................................164
20.2.1 USB SIE ..................................................................................................................165
20.2.2 USB SRAM..............................................................................................................166
20.2.3 Oscillator Lock .........................................................................................................168
20.2.4 Transceiver ..............................................................................................................168
20.2.5 USB Suspend ..........................................................................................................168
20.2.6 Regulator .................................................................................................................169
20.3.1 USB_SOF0 Register ...............................................................................................171
20.3.2 USB_CR0 Register..................................................................................................171
20.3.3 USBIO_CR0 Register..............................................................................................172
20.3.4 USBIO_CR1 Register..............................................................................................172
20.3.5 EP0_CR Register ....................................................................................................173
20.3.6 EP0_CNT Register ..................................................................................................174
20.3.7 EP0_DRx Register ..................................................................................................174
20.3.8 EPx_CNT1 Register ................................................................................................175
20.3.9 EPx_CNT0 Register ................................................................................................176
20.3.10 EPx_CR0 Register ..................................................................................................177
20.3.11 PMAx_WA Register .................................................................................................178
20.3.12 PMAx_DR Register .................................................................................................179
20.3.13 PMAx_RA Register..................................................................................................180
20.3.14 USB_CR1 Register..................................................................................................180
18.2.2.1 SPI Master Data Register Definitions........................................................148
18.2.2.2 SPI Slave Data Register Definitions..........................................................148
18.2.3.1 SPI Control Register Definitions................................................................149
18.2.4.1 SPI Configuration Register Definitions ......................................................150
20.2.2.1 PSoC Memory Arbiter ...............................................................................166
20.2.5.1 Using Standby I2C-USB Sleep Mode for USB Suspend...........................169
20.2.5.2 Using Standby or Deep Sleep Modes for USB Suspend ..........................169
20.2.5.3 Wakeup from Suspend..............................................................................169
161
165
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