CY8CTST200-32LQXIT Cypress Semiconductor Corp, CY8CTST200-32LQXIT Datasheet - Page 88
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CY8CTST200-32LQXIT
Manufacturer Part Number
CY8CTST200-32LQXIT
Description
CY8CTST200-32LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-32LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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For typical capacitances, the IDAC current can be config-
ured so that the average voltage on the analog global does
not change. This can be done in firmware using a succes-
sive approximation to find the IDAC setting that causes the
global net to remain relatively stable for the load capaci-
tance. After this baseline is set, a small increase in sense
capacitance causes the global net to slowly discharge,
eventually crossing the comparator threshold. The config-
urable low pass filter is designed to filter the ripple on the
global net, leaving the average voltage that indicates capac-
itance change. Firmware can read the comparator state after
a pre-selected time to see if a large enough change has
occurred to trip the comparator in that time. This approach is
well suited to quickly detecting a capacitive button press.
Alternately, capacitance can be accurately measured by
going through the complete successive approximation pro-
cedure. The final IDAC setting gives a measurement of
capacitance.
The delay between starting the pin switching and reading
the comparator can be set by a firmware delay, or by using
the 6-bit counter in the TrueTouch logic to generate an inter-
rupt.
Figure 11-8. First Phase of Successive Approximation
TrueTouch Module
88
Comparator
Vr
M8C Read
Reference
IDAC
Buffer
Mux
Mux
I
OUT
Filter
LP
Vr
Conn. to
Ground
Closed
CSCLK
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
C
INTERNAL
CS1
CS2
CSN
Figure 11-9. Second Phase of Successive Approximation
11.1.1.4
The negative charge integration method operates by initial-
izing an integration capacitor to a positive voltage, then dis-
connecting this driver. The integration capacitor voltage
decays through connection with an external sense capacitor
that is continuously switched between ground and the inte-
gration capacitor. The number of cycles required to reduce
the voltage on the integration capacitor to a target value
gives
Figure
The hardware supports the use of either pin P0[1] or P0[3]
for the external integration capacitor.
Comparator
Vr
Reference
M8C Read
IDAC
11-10.
a
Buffer
measure
Negative Charge Integration
Mux
Mux
I
OUT
Filter
LP
of
Vr
the
Conn. to
Closed
sense
Bus
CSCLK
capacitance.
C
INTERNAL
CS1
CS2
CSN
See
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