CY8CTST200-32LQXIT Cypress Semiconductor Corp, CY8CTST200-32LQXIT Datasheet - Page 8
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CY8CTST200-32LQXIT
Manufacturer Part Number
CY8CTST200-32LQXIT
Description
CY8CTST200-32LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-32LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Contents
Section D: System Resources
8
12. I/O Analog Multiplexer
13. Comparators
14. Digital Clocks
15. I2C Slave
11.2 Register Definitions ............................................................................................................... 92
11.3 Timing Diagrams .................................................................................................................... 97
12.1 Architectural Description......................................................................................................... 99
12.2 Register Definitions ..............................................................................................................100
13.1 Architectural Description ......................................................................................................101
13.2 Register Definitions .............................................................................................................103
14.1 Architectural Description.......................................................................................................109
14.2 Register Definitions ..............................................................................................................112
15.1 Architectural Description.......................................................................................................117
15.2 Application Overview ............................................................................................................118
11.1.2 IDAC .......................................................................................................................... 90
11.1.3 TrueTouch Counter ................................................................................................... 90
11.2.1 CS_CR0 Register ..................................................................................................... 92
11.2.2 CS_CR1 Register ..................................................................................................... 93
11.2.3 CS_CR2 Register ..................................................................................................... 93
11.2.4 CS_CR3 Register ..................................................................................................... 94
11.2.5 CS_CNTL Register ................................................................................................... 94
11.2.6 CS_CNTH Register .................................................................................................. 94
11.2.7 CS_STAT Register ................................................................................................... 95
11.2.8 CS_TIMER Register ................................................................................................. 95
11.2.9 CS_SLEW Register .................................................................................................. 96
11.2.10 PRS_CR Register ..................................................................................................... 96
11.2.11 IDAC_D Register ...................................................................................................... 97
12.2.1 MUX_CRx Registers ...............................................................................................100
13.2.1 CMP_RDC Register ...............................................................................................103
13.2.2 CMP_MUX Register ...............................................................................................103
13.2.3 CMP_CR0 Register ................................................................................................104
13.2.4 CMP_CR1 Register ................................................................................................104
13.2.5 CMP_LUT Register ................................................................................................104
14.1.1 Internal Main Oscillator............................................................................................109
14.1.2 Internal Low Speed Oscillator.................................................................................. 110
14.1.3 External Clock ......................................................................................................... 110
14.2.1 USB_MISC_CR Register ........................................................................................ 112
14.2.2 OUT_P0 Register ................................................................................................... 113
14.2.3 OUT_P1 Register ................................................................................................... 113
14.2.4 OSC_CR0 Register ................................................................................................ 113
14.2.5 OSC_CR2 Register ................................................................................................ 115
15.1.1 Basic I2C Data Transfer .......................................................................................... 118
15.2.1 Slave Operation....................................................................................................... 118
15.2.2 EZI2C Mode ............................................................................................................ 119
11.1.1.5 Sigma Delta................................................................................................. 89
11.1.3.1 Operation .................................................................................................... 91
14.1.3.1 Switch Operation .......................................................................................110
101
109
117
105
99
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