CY8CTST200-32LQXIT Cypress Semiconductor Corp, CY8CTST200-32LQXIT Datasheet - Page 84
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CY8CTST200-32LQXIT
Manufacturer Part Number
CY8CTST200-32LQXIT
Description
CY8CTST200-32LQXIT
Manufacturer
Cypress Semiconductor Corp
Series
TrueTouch™r
Datasheet
1.CY8CTST200-16LGXI.pdf
(308 pages)
Specifications of CY8CTST200-32LQXIT
Applications
Touchscreen Controller
Core Processor
M8C
Program Memory Type
FLASH (32 kB)
Controller Series
CY8CT
Ram Size
2K x 8
Interface
I²C, SPI, UART/USART, USB
Number Of I /o
28
Voltage - Supply
1.8 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
32-UQFN Exposed Pad, 32-HUQFN, 32-SQFN
Processor Series
CY8CTxx2xx
Core
M8C
Data Bus Width
8 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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Section C: TrueTouch System
TrueTouch Register Summary
The table below lists all the PSoC registers for the TrueTouch system in address order within their system resource configura-
tion. The bits that are grayed out are reserved bits. If these bits are written, always write them with a value of ‘0’.
Summary Table of the TrueTouch Registers
84
0,A0h
0,A1h
0,A2h
0,A3h
0,A4h
0,A5h
0,A6h
0,A7h
0,A8h
0,A9h
0,FDh
0,61h
1,D8h
1,D9h
1,DAh
1,DBh
1,DFh
0,78h
0,79h
0,7Ah
0,7Bh
0,7Ch
LEGEND
#
R Read register or bit(s).
W Write register or bit(s).
Address
Access is bit specific. Refer to the
CS_CR0
CS_CR1
CS_CR2
CS_CR3
CS_CNTL
CS_CNTH
CS_STAT
CS_TIMER
CS_SLEW
PRS_CR
IDAC_D
AMUX_CFG
MUX_CR0
MUX_CR1
MUX_CR2
MUX_CR3
MUX_CR4
CMP_RDC
CMP_MUX
CMP_CR0
CMP_CR1
CMP_LUT
Name
CS_CLK_OU
CHAIN
CINT1
Bit 7
INS
T
CSOUT[1:0]
Register Reference chapter on page 187
INP1[1:0]
IRANGE
CS_CLK_IN
REFMUX
CPIN1
COLS
Bit 6
V
CLKSEL[1:0]
IO ANALOG MULTIPLEXER REGISTERS (page 100)
LUT1[3:0]
PSoC CY8CTMG20x and CY8CTST200 TRM, Document No. 001-53603 Rev. *C
TRUETOUCH MODULE REGISTERS (page 92)
COMPARATOR REGISTERS (page 103)
PRS_12BIT
REFMODE
IDACDIR
PRSCLK
CMP1D
CRST1
MODE
COHS
CSD_
PRX_
Bit 5
INN1[1:0]
FastSlew[6:0]
CSD_CS_
IDAC_EN
CMP1EN
RLOCLK
REF_EN
PRS_EN
CMP0D
CDS1
Bit 4
CLK
PPS
for additional information.
DACDATA[7:0]
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
ENABLE[7:0]
Data[7:0]
Data[7:0]
Timer Count Value[6:0]
PRESCALE_
CIN_EN
MODE
CINT0
CSD_
Bit 3
INM
BYP
INV
ICAPEN[1:0]
LPFilt[1:0]
INP0[1:0]
PXD_EN
COLM
CPIN0
Bit 2
ENABLE[3:0]
PRESCALE_CLK_DIV[2:0]
MODE[1:0]
LUT0[3:0]
INSEL[2:0]
CIP_EN
CMP1L
CRST0
COHM
Bit 1
LPF_EN[1:0]
INTCAP[1:0]
INN0[1:0]
CMP0EN
RO_EN
CMP0L
FS_EN
CDS0
Bit 0
PPM
EN
Access
RW : 00
RW : 00
RW : 00
RW : 00
RO : 00
RO : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 00
RW : 0
RW : 0
# : 00
# : 0
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