CY8C3865LTI-014 Cypress Semiconductor Corp, CY8C3865LTI-014 Datasheet - Page 19

• Manufacturer Part Number: CY8C3865LTI-014
• Description: CY8C3865LTI-014
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ 3 CY8C38xxr

Specifications of CY8C3865LTI-014

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 67MHz
• Connectivity: EBI/EMI, I²C, LIN, SPI, UART/USART, USB
• Peripherals: CapSense, DMA, LCD, POR, PWM, WDT
• Number Of I /o: 38
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.71 V ~ 5.5 V
• Data Converters: A/D 2x20b, D/A 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Technology: CMOS
• Processing Unit: Microcontroller
• Operating Supply Voltage (min): 1.8V
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Package Type: QFN EP
• Screening Level: Industrial
• Pin Count: 68
• Mounting: Surface Mount
• Rad Hardened: No
• Processor Series: CY8C38
• Core: 8051
• Data Bus Width: 32 bit
• Data Ram Size: 8 KB
• Interface Type: I2C, SPI, UART, USB
• Maximum Clock Frequency: 67 MHz
• Number Of Programmable I/os: 28 to 72
• Number Of Timers: 4
• Operating Supply Voltage: 0.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Controller Family/series: (8051) PSOC 3
• No. Of I/o's: 38
• Eeprom Memory Size: 1KB
• Ram Memory Size: 4KB
• Cpu Speed: 67MHz
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.6 Memory Map
The CY8C38 8051 memory map is very similar to the MCS-51
memory map.
5.6.1 Code Space
The CY8C38 8051 code space is 64 KB. Only main flash exists
in this space. See the
5.6.2 Internal Data Space
The CY8C38 8051 internal data space is 384 bytes, compressed
within a 256-byte space. This space consists of 256 bytes of
RAM (in addition to the SRAM mentioned in
18) and a 128-byte space for special function registers (SFR).
See
registers R0-R7. The next 16 bytes are bit-addressable.
Document Number: 001-11729 Rev. *O
Figure
5-2. The lowest 32 bytes are used for 4 banks of
PHUB
Flash Program Memory
Data,
and Control
Signals
Data,
Signals
Data,
and Control
Signals
Address,
Address,
and Control
Address,
IO IF
Static RAM
PRELIMINARY
EM Control
Signals
on page 18.
Figure 5-1. EMIF Block Diagram
EMIF
UDB
on page
Data Signals
Address Signals
Control Signals
Signals
Other
Control
Figure 5-2. 8051 Internal Data Space
PSoC
0x1F
0x2F
0x7F
0xFF
0x00
0x20
0x30
0x80
DSI to Port
Control
DSI Dynamic Output
®
Upper Core RAM Shared
PORTs
PORTs
PORTs
(indirect addressing)
I/O
I/O
I/O
3: CY8C38 Family Datasheet
with Stack Space
Lower Core RAM Shared with Stack Space
External _ MEM_ ADDR [23:0]
External _ MEM_ DATA[15:0]
(direct and indirect addressing)
4 Banks, R0-R7 Each
Bit-Addressable Area
Control
Special Function Registers
(direct addressing)
SFR
Page 19 of 117
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