CY7C68053-56BAXIT Cypress Semiconductor Corp, CY7C68053-56BAXIT Datasheet - Page 33

• Manufacturer Part Number: CY7C68053-56BAXIT
• Description: CY7C68053-56BAXIT
• Manufacturer: Cypress Semiconductor Corp
• Series: MoBL-USB™r

Specifications of CY7C68053-56BAXIT

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB
• Number Of I /o: 56
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3687 - KIT DEV MOBL-USB FX2LP18
• Lead Free Status / Rohs Status: Details

9.13 Sequence Diagram
Various sequence diagrams and examples are presented in this section.
9.13.1 Single and Burst Synchronous Read Example
Figure 20
signals during a synchronous FIFO read using IFCLK as the
synchronizing clock. The diagram illustrates a single read
followed by a burst read.
■
■
■
Document # 001-06120 Rev *J
At t = 0 the FIFO address is stable and the signal SLCS is
asserted (SLCS may be tied low in some applications).
Note t
IFCLK is running at 48 MHz, the FIFO address setup time is
more than one IFCLK cycle.
At t = 1, SLOE is asserted. SLOE is an output enable only
whose sole function is to drive the data bus. The data that is
driven on the bus is the data that the internal FIFO pointer is
currently pointing to. In this example, it is the first data value in
the FIFO.
Note The data is prefetched and driven on the bus when SLOE
is asserted.
At t = 2, SLRD is asserted. SLRD must meet the setup time of
t
the IFCLK) and maintain a minimum hold time of t
from the IFCLK edge to the deassertion of the SLRD signal).
SRD
FIFOADR
FLAGS
FIFO POINTER
DATA
FIFO DATA BUS
IFCLK
SLRD
SLCS
SLOE
(time from asserting the SLRD signal to the rising edge of
SFA
shows the timing relationship of the SLAVE FIFO
has a minimum of 25 ns. This means that when
Not Driven
t=0
IFCLK
N
Figure 20. Slave FIFO Synchronous Read Sequence and Timing Diagram
t=1
SLOE
t
SFA
Figure 21. Slave FIFO Synchronous Sequence of Events Diagram
t
OEon
Data Driven: N
t=2
Driven: N
t
SRD
IFCLK
N
t
IFCLK
t
XFD
t=3
t
RDH
SLRD
t
XFLG
t
OEoff
N+1
t=4
t
N+1
FAH
IFCLK
N+1
RDH
SLOE
SLRD
(time
Not Driven
IFCLK
t
T=0
N+1
SFA
t
■
The same sequence of events is shown for a burst read and is
marked with the time indicators of T = 0 through 5.
Note For the burst mode, the SLRD and SLOE are left asserted
during the entire duration of the read. In the burst read mode,
when SLOE is asserted, data indexed by the FIFO pointer is on
the data bus. During the first read cycle on the rising edge of the
clock, the FIFO pointer is updated and increments to point to
address N+1. For each subsequent rising edge of IFCLK while
the SLRD is asserted, the FIFO pointer is incremented and the
next data value is placed on the data bus.
OEon
SLOE
If the SLCS signal is used, it must be asserted before SLRD
(that is, the SLCS and SLRD signals must both be asserted to
start a valid read condition).
The FIFO pointer is updated on the rising edge of the IFCLK
while SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of t
IFCLK) the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
must also be asserted.
T=2
>= t
T=1
N+1
IFCLK
N+1
SRD
N+1
SLRD
t
XFD
N+2
N+2
IFCLK
N+2
N+3
N+3
IFCLK
XFD
t
XFD
(measured from the rising edge of
N+4
N+4
IFCLK
N+3
SLRD
[16]
t
>= t
XFD
RDH
N+4
N+4
IFCLK
t
N+4
OEoff
CY7C68053
SLOE
T=3
T=4
t
FAH
Page 33 of 42
Not Driven
IFCLK
N+4
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