CY7C68053-56BAXI Cypress Semiconductor Corp, CY7C68053-56BAXI Datasheet

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... Smart RAM ECC USB 1.1/2.0 Engine “Soft Configuration” FIFO and Endpoint Memory Easy Firmware Changes (Master or Slave Operation) • 198 Champion Court • San Jose CY7C68053 Microcontroller Master Abundant IO Additional IOs (24) General GPIF Programmable I/F RDY (2) CTL (3) To Baseband Processors/ ...

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... External FIFO Interface ............................................... 9 GPIF ............................................................................ 9 [6] ................................................................... 10 ECC Generation USB Uploads and Downloads ................................... 10 Autopointer Access ................................................... Controller ............................................................. 10 Pin Assignments ............................................................ 11 CY7C68053 Pin Descriptions ................................... 13 Register Summary .......................................................... 17 Absolute Maximum Ratings .......................................... 24 Operating Conditions ..................................................... 24 DC Characteristics ........................................................ 24 Document # 001-06120 Rev *J AC Electrical Characteristics ........................................ 25 USB Transceiver ....................................................... 25 GPIF Synchronous Signals ....................................... 25 Slave FIFO Synchronous Read ................................. 26 Slave FIFO Asynchronous Read ...

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... Cypress Semiconductor Corporation’s MoBL-USB™ FX2LP18 (CY7C68053 low voltage (1.8 V) version of the EZ-USB FX2LP (CY7C68013A), which is a highly integrated, low power USB 2.0 microcontroller. By integrating the USB 2.0 transceiver, serial interface engine (SIE), enhanced 8051 microcontroller, and a programmable peripheral interface in a single chip, ...

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... When a USB interrupt is asserted, the FX2LP18 pushes the program counter onto its stack then jumps to address 0x0043, where it expects to find a ‘jump’ instruction to the USB interrupt service routine. The FX2LP18 jump instruction is encoded as shown in on page 5. CY7C68053 SCON1 PSW ...

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... EP8 OUT was pinged and it NAK’d Bus errors exceeded the programmed limit Reserved Reserved ISO EP2 OUT PID sequence error ISO EP4 OUT PID sequence error ISO EP6 OUT PID sequence error ISO EP8 OUT PID sequence error CY7C68053 Notes Page [+] Feedback ...

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... The input pin, RESET#, resets the FX2LP18 when asserted. This pin has hysteresis and is active LOW. When a crystal is used with the CY7C68053, the reset period must allow for the stabilization of the crystal and the PLL. This reset period must be approximately 5 ms after VCC has reached 3 the crystal input pin is driven by a clock signal the internal PLL stabilizes in 200 μ ...

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... EP8 can be double buffered, while EP2 and 6 can be double, triple, or quad buffered. For high speed endpoint configuration options, see 3.12.3 Setup Data Buffer A separate 8-byte buffer at 0xE6B8-0xE6BF holds the setup data from a CONTROL transfer. CY7C68053 4 kBytes EP2-EP8 buffers (8 x 512) 2 kBytes RESERVED 64 Bytes EP1IN ...

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... CY7C68053 EP2 EP2 EP2 EP2 EP2 512 1024 1024 1024 ...

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... GPIF The GPIF is a flexible 8- or 16-bit parallel interface driven by a user programmable finite state machine. It allows the CY7C68053 to perform local bus mastering, and can implement a wide variety of protocols such as ATA interface, parallel printer port, and Utopia. The GPIF has three programmable control outputs (CTL), and two general purpose ready inputs ...

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... If no EEPROM is connected to the I is required by an external processor. This is because the FX2LP18 comes out of reset with the DISCON bit set, so the device will not enumerate without an EEPROM (C2 load) or EEPROM emulation. CY7C68053 [ port that is driven by two internal 2 C port operates in master mode only. ...

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... CTL2 INT0#/PA0 INT0#/PA0 INT0#/PA0 INT1#/PA1 INT1#/PA1 INT1#/PA1 PA2 PA2 SLOE WU2/PA3 WU2/PA3 WU2/PA3 PA4 FIFOADR0 PA4 PA5 PA5 FIFOADR1 PA6 PKTEND PA6 PA7 PA7 PA7/FLAGD/SLCS# CY7C68053 2 C bus using 2 C master 2 C slave. Page [+] Feedback ...

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... Figure 7. CY7C68053 56-pin VFBGA Pin Assignment - Top View Document # 001-06120 Rev * CY7C68053 Page [+] Feedback ...

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... CY7C68053 Pin Descriptions [9] Table 7. FX2LP18 Pin Descriptions 56 VFBGA Name Type 2D AV Power Power CC 2F AGND Ground 1F AGND Ground 1E DMINUS I/O/Z 2E DPLUS I/O/Z 8B RESET# Input 1C XTALIN Input 2C XTALOUT Output 2B CLKOUT O/Z Port A 8G PA0 or I/O/Z INT0# 6G PA1 or I/O/Z INT1# 8F PA2 or I/O/Z ...

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... Multiplexed pin whose function is selected by IFCONFIG[1:0]. (PB6) PB6 is a bidirectional I/O port pin. FD[6] is the bidirectional FIFO/GPIF data bus. I Multiplexed pin whose function is selected IFCONFIG[1:0]. (PB7) PB7 is a bidirectional I/O port pin. FD[7] is the bidirectional FIFO/GPIF data bus. CY7C68053 Description Page [+] Feedback ...

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... IFCLK also serves as a timing reference for all slave FIFO control signals and GPIF. When internal clocking is used (IFCONFIG the IFCLK pin can be configured to output MHz by bits IFCONFIG.5 and IFCONFIG.6. IFCLK may be inverted, whether internally or externally sourced, by setting the bit IFCONFIG.4 =1. CY7C68053 Description Page [+] Feedback ...

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... VCC. Connect this pin to 1.8V power source. (Supplies power to internal analog 1.8 V circuits.) N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. N/A Ground. CY7C68053 Description ® chip from suspending. This pin or V with a 2.2K–10K pull up CC_IO with a 2.2K–10K pull up CC_IO CC Page [+] Feedback ...

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... PL6 PL5 PL4 PL7 PL6 PL5 PL4 LINE15 LINE14 LINE13 LINE12 LINE11 LINE7 LINE6 LINE5 LINE4 LINE3 CY7C68053 Default xxxxxxxx RW Reserved Reserved Reserved 00000000 R CLKINV CLKOE 8051RES 00000010 rrbbbbbr GSTATE IFCFG1 IFCFG0 10000000 RW FLAGA2 FLAGA1 FLAGA0 00000000 RW FLAGC2 FLAGC1 FLAGC0 00000000 RW ...

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... EP8 EP6 0 0 EP8 EP6 EP8 EP6 EP4 EP2 EP8 EP6 EP4 EP2 0 EP0ACK HSGRANT URES SUSP 0 EP0ACK HSGRANT URES SUSP CY7C68053 Default COL0 LINE17 LINE16 00000000 R LINE10 LINE9 LINE8 00000000 R LINE2 LINE1 LINE0 00000000 R COL0 0 0 00000000 R 0 PFC9 PFC8 ...

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... BC7/SKIP BC6 BC5 BC4 BC3 BC7/SKIP BC6 BC5 BC4 BC3 BC7/SKIP BC6 BC5 BC4 BC3 HSNAK CY7C68053 Default Access EP1IN EP0OUT EP0IN 00000000 RW EP1IN EP0OUT EP0IN GPIFWF GPIFDONE 00000000 GPIFWF GPIFDONE 000000xx ERRLIMIT 00000000 ERRLIMIT 0000000x bbbbrrrb LIMIT2 LIMIT1 LIMIT0 xxxx0100 rrrrbbbb ...

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... CTLTOGL SUSTAIN TC31 TC30 TC29 TC28 TC23 TC22 TC21 TC20 TC15 TC14 TC13 TC12 TC7 TC6 TC5 TC4 CY7C68053 Default 0 0 BUSY STALL 00000000 bbbbbbrb FULL EMPTY 0 STALL 00101000 rrrrrrrb FULL EMPTY 0 STALL 00101000 rrrrrrrb FULL EMPTY 0 STALL 00000100 rrrrrrrb FULL ...

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... D15 D14 D13 D12 D11 INTRDY SAS TCXRDY5 DISCON 0 0 CY7C68053 Default Access 0 0 FS1 FS0 00000000 FIFO2FLAG 00000000 xxxxxxxx FS1 FS0 00000000 FIFO4FLAG 00000000 xxxxxxxx FS1 FS0 00000000 FIFO6FLAG 00000000 xxxxxxxx FS1 FS0 00000000 FIFO8FLAG 00000000 xxxxxxxx W D10 D9 D8 xxxxxxxx RW ...

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... PS1 PT2 PS0 PT1 DONE D15 D14 D13 D12 D11 CY7C68053 Default Access xxxxxxxx 00000111 00000000 RW A10 A9 A8 00000000 00000000 RW A10 A9 A8 00000000 SEL 00000000 IDLE 00110000 RW IT1 IE0 IT0 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 RW D10 D9 D8 00000000 RW MD2 ...

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... D15 D14 D13 D12 D11 RS1 RS0 SMOD1 1 ERESI RESI INT6 EX6 EX5 PX6 PX5 CY7C68053 Default Access RB8_1 TI_1 RI_1 00000000 00000000 RW TR2 CT2 CPRL2 00000000 00000000 00000000 00000000 RW D10 D9 D8 00000000 00000000 01000000 00000000 RW EX4 EI²C EUSB 11100000 RW D2 ...

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... Load capacitors 12 pF Conditions 0.6*V 0< V < CC_IO OUT CC_IO I = –4 mA OUT Except D+/D– D+/D– Connected Disconnected CY7C68053 Min Typ Max Unit 3.00 3.3 3.60 V 1.71 1.8 3.60 V 1.71 1.8 1.89 V 1.71 1.8 1.89 ...

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... USB HS 8051 running, connected to USB FS ) 8051 running, connected to USB HS 8051 running, connected to USB FS V min = 3 IFCLK t SGA t SRY t RYH valid t t SGD DAH t XCTL N N+1 t XGD Description CY7C68053 Min Typ Max 5.0 200 [16] [16,17] Min Max Unit 20. ...

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... MHz IFCLK. x 18. IFCLK must not exceed 48 MHz. Document # 001-06120 Rev *J Description Min 20.83 2.9 3.7 3.2 4.5 [16] t IFCLK t t RDH SRD t XFLG N OEon XFD Description Min 20.83 18.7 2.15 CY7C68053 [17] Max Unit 200 13. OEoff [17] Max Unit 10.5 ns 10 ...

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... Slave FIFO asynchronous parameter values use internal IFCLK setting at 48 MHz. Document # 001-06120 Rev *J Description Min 20.83 12.7 3.7 2.15 t RDpwh t RDpwl t XFLG t XFD N N OEon OEoff [19] Description Min 2.15 CY7C68053 [17] Max Unit 200 10.5 ns 10.5 ns 13.5 ns 17.31 ns [16] Max Unit ...

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... FDH t Clock to FLAGS output propagation time XFLG Document # 001-06120 Rev *J t IFCLK t WRH t SWR SFD FDH t XFLG Description Min 20.83 18.1 10.64 Description Min 20.83 12.1 3.6 3.2 4.5 CY7C68053 [16] Z [17] Max Unit 9.5 ns [10] Max Unit 200 13.5 ns Page [+] Feedback ...

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... Clock to FLAGS output propagation delay XFLG Document # 001-06120 Rev *J t WRpwh t WRpwl t t FDH SFD t XFD Description Min t PEH t SPE t XFLG Description Min 20.83 14.6 Description Min 20.83 8.6 3.04 CY7C68053 [16] [19] Max Unit [16] [10] Max Unit 9.5 ns [10] Max Unit 200 ns ...

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... FX2LP18 failing to send the one byte/word short packet SFD FDH FDH FDH SFD SFD X-2 X-1 X-3 t PEpwh t PEpwl t XFLG [19] Description Min CY7C68053 [16] t FAH >= t WRH FDH SFD FDH SFD least one IFCLK cycle t SPE t PEH [16] Max Unit 50 ns ...

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... Table 22. Slave FIFO Address to Flags/Data Parameters Parameter t FIFOADR[1:0] to flags output propagation delay XFLG t FIFOADR[1:0] to FIFO data output propagation delay XFD Document # 001-06120 Rev *J t OEoff t OEon Description Min 2.15 t XFLG t XFD N N+1 Description Min CY7C68053 [16] Max Unit 10.5 ns 10.5 ns [16] Max Unit 10.7 ns 14.3 ns Page [+] Feedback ...

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... Figure 19. Slave FIFO Asynchronous Address Timing Diagram SLCS/FIFOADR [1:0] SLRD/SLWR/PKTEND Slave FIFO Asynchronous Address Parameters Parameter t FIFOADR[1:0] to SLRD/SLWR/PKTEND setup time SFA t RD/WR/PKTEND to FIFOADR[1:0] hold time FAH Document # 001-06120 Rev * SFA FAH [10] Description Min 20.83 t FAH t SFA [19] Description Min CY7C68053 [16] Max Unit 200 [16] Max Unit Page [+] Feedback ...

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... FIFO pointer is updated and increments to point to address N+1. For each subsequent rising edge of IFCLK while the SLRD is asserted, the FIFO pointer is incremented and the (time RDH next data value is placed on the data bus. CY7C68053 [16] t FAH >= t RDH T=3 ...

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... AUTOINLEN register). Refer to details about this timing. CY7C68053 [16] t FAH >= t ...

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... Note In burst read mode, during SLOE assertion, the data bus driven state and outputs the previous data. Once SLRD is asserted, the data from the FIFO is driven on the data bus (SLOE must also be asserted) and then the FIFO pointer is incremented. CY7C68053 [16] t FAH t ...

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... SLWR and the PKTEND signal at the same time. It must be designed to assert the PKTEND after SLWR is deasserted and meet the minimum deasserted pulse width. The FIFOADDR lines are to be held constant during the before the SFD PKTEND assertion. from XFLG CY7C68053 [16] t FAH t WRpwh T=9 t XFLG ...

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... For more information, visit the Cypress website at www.cypress.com and refer to the product summary page at http://www.cypress.com/products. Table 24. Key Features and Ordering Information Ordering Code CY7C68053-56BAXI Development Tool Kit CY3687 Ordering Code Definitions CY ...

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... Package Diagram The FX2LP18 is available in a 56-pin VFBGA package. Figure 26. 56 VFBGA (5 × 5 × 1.0 mm) 0.50 Pitch, 0.30 Ball BZ56 Document # 001-06120 Rev *J CY7C68053 001-03901 *C [+] Feedback [+] Feedback Page [+] Feedback ...

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... Maintain a solid ground plane under the DPLUS and DMINUS traces. Do not allow the plane to be split under these traces. ■ preferable to have no vias placed on the DPLUS or DMINUS trace routing. ■ Isolate the DPLUS and DMINUS traces from all other signal traces by no less than 10 mm. CY7C68053 Page [+] Feedback ...

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... Document # 001-06120 Rev *J 14. Document Conventions Units of Measure Table 26. Units of Measure Symbol Unit of Measure KHz kilohertz Mbytes megabytes MHz megahertz µA microampere µs microseconds µW microwatts mA milliampere mW milliwatts ns nanoseconds ppm parts per million pF picofarads V volts CY7C68053 Page [+] Feedback ...

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... Document History Page Document Title: CY7C68053 MoBL-USB™ FX2LP18 USB Microcontroller Document Number: 001-06120 Orig. of Submission Revision ECN Change ** 430449 OSG 03/03/06 *A 434754 OSG 03/24/06 *B 465471 OSG See ECN *C 484726 ARI See ECN *D 492009 OSG See ECN *E 500408 OSG See ECN ...

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... I2C Standard Specification as defined by Philips. MoBL-USB FX2LP18, EZ-USB FX2LP and ReNumeration are trademarks, and MoBL-USB is a registered trademark, of Cypress Semiconductor Corporation. All product and company names mentioned in this document are the trademarks of their respective holders. cypress.com/go/plc Revised October 28, 2010 CY7C68053 PSoC Solutions psoc.cypress.com/solutions PSoC 1 ...