CY7C68053-56BAXI Cypress Semiconductor Corp, CY7C68053-56BAXI Datasheet - Page 17

• Manufacturer Part Number: CY7C68053-56BAXI
• Description: IC,MICROCONTROLLER,8-BIT,8051 CPU,BGA,56PIN,PLASTIC
• Manufacturer: Cypress Semiconductor Corp
• Series: MoBL-USB™r

Specifications of CY7C68053-56BAXI

• Applications: USB Microcontroller
• Core Processor: 8051
• Program Memory Type: ROMless
• Controller Series: CY7C680xx
• Ram Size: 16K x 8
• Interface: I²C, USB
• Number Of I /o: 56
• Voltage - Supply: 1.71 V ~ 1.89 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-VFBGA
• Processor Series: CY7C68xx
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 16 KB
• Interface Type: I2C
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 24
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: CY3687 - KIT DEV MOBL-USB FX2LP18
• Lead Free Status / Rohs Status: Details

5. Register Summary
FX2LP18 register bit definitions are described in the MoBL-USB FX2LP18 TRM in greater detail.
Table 8. FX2LP18 Register Summary
Document # 001-06120 Rev *J
Hex
E400 128 WAVEDATA
E480 128 Reserved
E50D
E600
E601
E602
E603
E604
E605
E606
E607
E608
E609
E60A
E60B
E60C
E610
E611
E612
E613
E614
E615
E618
E619
E61A
E61B
E61C
E620
E621
E622
E623
E624
E625
E626
E627
E628
E629
E62A
E62B
Note
10. Read and writes to these registers may require synchronization delay, see MoBL-USB FX2LP18 Technical Reference Manual for ‘Synchronization Delay.’
Size Name
1
1
1
1
1
1
1
1
1
1
1
1
1
3
1
1
1
1
1
1
2
1
1
1
1
4
1
1
1
1
1
1
1
1
1
1
1
1
GPIF Waveform Memories
GENERAL CONFIGURATION
GPCR2
CPUCS
IFCONFIG
PINFLAGSAB
PINFLAGSCD
FIFORESET
BREAKPT
BPADDRH
BPADDRL
Reserved
FIFOPINPOLAR
REVID
REVCTL
UDMA
GPIFHOLDAMOUNT MSTB hold time
Reserved
ENDPOINT CONFIGURATION
EP1OUTCFG
EP1INCFG
EP2CFG
EP4CFG
EP6CFG
EP8CFG
Reserved
EP2FIFOCFG
EP4FIFOCFG
EP6FIFOCFG
EP8FIFOCFG
Reserved
EP2AUTOINLENH
EP2AUTOINLENL
EP4AUTOINLENH
]
EP4AUTOINLENL
EP6AUTOINLENH
]
EP6AUTOINLENL
EP8AUTOINLENH
]
EP8AUTOINLENL
ECCCFG
ECCRESET
ECC1B0
ECC1B1
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10]
[10
[10
[10
[10
Description
GPIF Waveform
descriptor 0, 1, 2, 3 data
General Purpose Configura-
tion Register 2
CPU Control and Status
Interface Configuration
(Ports, GPIF, Slave FIFOs)
Slave FIFO FLAGA and
FLAGB pin configuration
Slave FIFO FLAGC and
FLAGD pin configuration
Restore FIFOs to default
state
Breakpoint control
Breakpoint address H
Breakpoint address L
Reserved
Slave FIFO interface pins
polarity
Chip revision
Chip revision control
(for UDMA)
Endpoint 1-OUT
configuration
Endpoint 1-IN
configuration
Endpoint 2 configuration
Endpoint 4 configuration
Endpoint 6 configuration
Endpoint 8 configuration
Endpoint 2/Slave FIFO
configuration
Endpoint 4/Slave FIFO
configuration
Endpoint 6/Slave FIFO
configuration
Endpoint 8/Slave FIFO
configuration
Endpoint 2 AUTOIN
packet length H
Endpoint 2 AUTOIN
packet length L
Endpoint 4 AUTOIN
packet length H
Endpoint 4 AUTOIN
packet length L
Endpoint 6 AUTOIN
packet length H
Endpoint 6 AUTOIN
packet length L
Endpoint 8 AUTOIN
packet length H
Endpoint 8 AUTOIN
packet length L
ECC Configuration
ECC Reset
ECC1 Byte 0 address
ECC1 Byte 1 address
IFCLKSRC
Reserved
FLAGD3
FLAGB3
NAKALL
LINE15
VALID
VALID
VALID
VALID
VALID
VALID
LINE7
A15
PL7
PL7
PL7
PL7
rv7
b7
D7
A7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
3048MHZ
Reserved
FLAGD2
FLAGB2
LINE14
INFM1
INFM1
INFM1
INFM1
LINE6
A14
DIR
DIR
DIR
DIR
PL6
PL6
PL6
PL6
D6
rv6
b6
A6
0
0
0
0
0
0
0
0
0
0
0
0
0
0
x
PORTCSTB
Reserved
IFCLKOE
FLAGD1
PKTEND
FLAGB1
LINE13
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
TYPE1
LINE5
OEP1
OEP1
OEP1
OEP1
A13
PL5
PL5
PL5
PL5
D5
rv5
b5
A5
0
0
0
0
0
0
0
0
0
0
x
FULL_SPEED
IFCLKPOL
AUTOOUT
AUTOOUT
AUTOOUT
AUTOOUT
CLKSPD1
FLAGB0
FLAGD0
LINE12
_ONLY
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
TYPE0
SLOE
LINE4
A12
PL4
PL4
PL4
PL4
rv4
b4
D4
A4
0
0
0
0
0
0
0
0
0
0
x
CLKSPD0
Reserved
FLAGA3
FLAGC3
AUTOIN
AUTOIN
AUTOIN
AUTOIN
ASYNC
BREAK
LINE11
LINE3
SLRD
SIZE
SIZE
EP3
A11
PL3
PL3
PL3
PL3
D3
A3
rv3
b3
0
0
0
0
0
0
0
0
0
0
0
0
x
ZEROLENIN
ZEROLENIN
ZEROLENIN
ZEROLENIN
BPPULSE
Reserved
GSTATE
FLAGC2
FLAGA2
CLKINV
LINE10
SLWR
LINE2
PL10
PL10
EP2
A10
PL2
PL2
PL2
PL2
D2
rv2
b2
A2
0
0
0
0
0
0
0
0
0
0
0
0
x
HOLDTIME1 HOLDTIME0 00000000 rrrrrrbb
Reserved
FLAGC1
FLAGA1
IFCFG1
dyn_out
CLKOE
BPEN
LINE9
LINE1
BUF1
BUF1
EP1
PL9
PL1
PL9
PL1
PL9
PL1
PL9
PL1
rv1
b1
D1
A9
A1
EF
0
0
0
0
0
0
0
0
0
0
x
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
WORDWIDE 00000101 rbbbbbrb
Reserved 00000000 R
8051RES 00000010 rrbbbbbr
FLAGA0
FLAGC0
IFCFG0
enh_pkt
ECCM
LINE8
LINE0
BUF0
BUF0
CY7C68053
EP0
PL8
PL0
PL8
PL0
PL8
PL0
PL8
PL0
D0
rv0
b0
A8
A0
FF
0
0
0
0
0
0
x
Page 17 of 42
Default
xxxxxxxx RW
10000000 RW
00000000 RW
00000000 RW
xxxxxxxx W
00000000 rrrrbbbr
xxxxxxxx RW
xxxxxxxx RW
00000000 rrrrrrbb
00000000 rrbbbbbb
RevA
00000001
00000000 rrrrrrbb
10100000 brbbrrrr
10100000 brbbrrrr
10100010 bbbbbrbb
10100000 bbbbrrrr
11100010 bbbbbrbb
11100000 bbbbrrrr
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000010 rrrrrbbb
00000000 RW
00000010 rrrrrrbb
00000000 RW
00000000 rrrrrrrb
00000000 W
00000000 R
00000000 R
Access
R
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