CY7C1360C-200BGCT Cypress Semiconductor Corp, CY7C1360C-200BGCT Datasheet - Page 23

• Manufacturer Part Number: CY7C1360C-200BGCT
• Description: CY7C1360C-200BGCT
• Manufacturer: Cypress Semiconductor Corp

Specifications of CY7C1360C-200BGCT

• Format - Memory: RAM
• Memory Type: SRAM - Synchronous
• Memory Size: 9M (256K x 36)
• Speed: 200MHz
• Interface: Parallel
• Voltage - Supply: 3.135 V ~ 3.6 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 119-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Switching Characteristics
Over the Operating Range
Document Number: 38-05540 Rev. *K
t
Clock
t
t
t
Output Times
t
t
t
t
t
t
t
Set-up Times
t
t
t
t
t
t
Hold Times
t
t
t
t
t
t
Notes
POWER
CYC
CH
CL
CO
DOH
CLZ
CHZ
OEV
OELZ
OEHZ
AS
ADS
ADVS
WES
DS
CES
AH
ADH
ADVH
WEH
DH
CEH
21. Timing reference level is 1.5 V when V
22. Test conditions shown in (a) of AC Test Loads unless otherwise noted.
23. This part has a voltage regulator internally; t
24. t
25. At any given voltage and temperature, t
26. This parameter is sampled and not 100% tested.
Parameter
can be initiated.
data bus. These specifications do not imply a bus contention condition, but reflect parameters guaranteed over worst case user conditions. Device is designed
to achieve high Z prior to low Z under the same system conditions.
CHZ
, t
CLZ
,t
OELZ
, and t
V
Clock cycle time
Clock HIGH
Clock LOW
Data output valid after CLK rise
Data output hold after CLK rise
Clock to low Z
Clock to high Z
OE LOW to output valid
OE LOW to output low Z
OE HIGH to output high Z
Address setup before CLK rise
ADSC, ADSP setup before CLK rise
ADV setup before CLK rise
GW, BWE, BW
Data input setup before CLK rise
Chip enable setup before CLK rise
Address hold after CLK rise
ADSP, ADSC hold after CLK rise
ADV hold after CLK rise
GW, BWE, BW
Data input hold after CLK rise
Chip enable hold after CLK rise
DD
(Typical) to the first access
OEHZ
are specified with AC test conditions shown in part (b) of AC Test Loads. Transition is measured ± 200 mV from steady-state voltage.
[21, 22]
[24, 25, 26]
Description
[24, 25, 26]
X
X
setup before CLK rise
hold after CLK rise
DDQ
OEHZ
POWER
= 3.3 V and is 1.25 V when V
is less than t
[24, 25, 26]
[24, 25, 26]
is the time that the power needs to be supplied above V
[23]
OELZ
and t
CHZ
is less than t
DDQ
1.25
1.25
1.25
Min
4.0
1.8
1.8
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
= 2.5 V.
1
–
–
0
–
–250
CLZ
to eliminate bus contention between SRAMs when sharing the same
Max
2.8
2.8
2.8
2.8
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.25
1.25
1.25
Min
5.0
2.0
1.5
1.5
0.5
2.0
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1
–
–
0
–
DD
(minimum) initially before a read or write operation
–200
CY7C1360C, CY7C1362C
Max
3.0
3.0
3.0
3.0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
1.25
1.25
1.25
Min
6.0
2.4
2.4
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
1
–
–
0
–
–166
Max
3.5
3.5
3.5
3.5
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
Page 23 of 34
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