CY14B101LA-ZS45XIT Cypress Semiconductor Corp, CY14B101LA-ZS45XIT Datasheet - Page 16

CY14B101LA-ZS45XIT

CY14B101LA-ZS45XIT

Manufacturer Part Number
CY14B101LA-ZS45XIT
Description
CY14B101LA-ZS45XIT
Manufacturer
Cypress Semiconductor Corp
Datasheet

Specifications of CY14B101LA-ZS45XIT

Format - Memory
RAM
Memory Type
NVSRAM (Non-Volatile SRAM)
Memory Size
1M (128K x 8)
Speed
45ns
Interface
Parallel
Voltage - Supply
2.7 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Package / Case
44-TSOP II
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Hardware STORE Cycle
Switching Waveforms
Document #: 001-42879 Rev. *K
Notes
t
t
t
Parameter
DHSB
PHSB
SS
40. This is the amount of time it takes to take action on a soft sequence command. V
41. Commands such as STORE and RECALL lock out I/O until operation is complete which further increases this time. See the specific command.
42. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware STORE takes place.
[40, 41]
DQ (Data Out)
HSB (OUT)
HSB (OUT)
Address
Write latch not set
Write latch set
HSB (IN)
HSB (IN)
HSB to output active time when write latch not set
Hardware STORE pulse width
Soft sequence processing time
V
CE
CC
RWI
RWI
Address #1
t
SA
t
DELAY
Description
Soft Sequence
t
t
PHSB
DELAY
t
PHSB
Command
Figure 15. Soft Sequence Processing
Figure 14. Hardware STORE Cycle
Address #6
t
DHSB
t
CW
t
SS
t
STORE
t
DHSB
CC
Address #1
Min
power must remain HIGH to effectively register command.
15
20 ns
Soft Sequence
100 kOhm resistor,
SRAM is disabled as long as HSB (IN) is driven low.
HSB pin is driven high to
HSB driver is disabled
Command
Max
100
20
[42]
[40, 41]
Address #6
Min
15
25 ns
t
CW
t
LZHSB
t
Max
100
HHHD
25
V
CC
t
SS
only by Internal
Min
CY14B101NA
CY14B101LA
15
45 ns
Page 16 of 26
Max
100
25
Unit
ns
ns
μs
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