CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 40

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

15. APPENDIX B: CHANNEL STATUS
15.1 AES3 Channel Status (C) Bit
The CS8415A contains sufficient RAM to store a
full block of C data for both A and B channels (192
x 2 = 384 bits), and also 384 bits of U information.
The user may read from these buffer RAMs
through the control port.
The buffering scheme involves 2 block-sized buff-
ers, named D and E, as shown in Figure 17. The
MSB of each byte represents the first bit in the se-
rial C data stream. For example, the MSB of byte 0
(which is at control port address 32) is the consum-
er/professional bit for channel status block A.
The first buffer (D) accepts incoming C data from
the AES receiver. The 2nd buffer (E) accepts entire
blocks of data from the D buffer. The E buffer is
also accessible from the control port, allowing
reading of the C data.
15.2 Accessing the E buffer
The user can monitor the incoming data by reading
the E buffer, which is mapped into the register
space of the CS8415A, through the control port.
40
From
AES3
Receiver
Figure 17. Channel Status Data Buffer Structure
AND USER DATA BUFFER
MANAGEMENT
Management
Received
Data
Buffer
D
8-bits
A
Control Port
words
E
8-bits
24
B
The user can configure the interrupt enable register
to cause interrupts to occur whenever D to E buffer
transfers occur. This allows determination of the al-
lowable time periods to interact with the E buffer.
Also provided is a D to E inhibit bit. This may be
used whenever “long” control port interactions are
occurring.
A flowchart for reading the E buffer is shown in
Figure 18. Since a D to E interrupt just occurred af-
ter reading, there is a substantial time interval until
the next D to E transfer (approximately 24 frames
worth of time). This is usually plenty of time to ac-
cess the E data without having to inhibit the next
transfer.
15.2.1 Reserving the first 5 bytes in the E
D to E buffer transfers periodically overwrite the
data stored in the E buffer. The CS8415A has the
capability of reserving the first 5 bytes of the E
buffer for user writes only. When this capability is
in use, internal D to E buffer transfers will NOT af-
fect the first 5 bytes of the E buffer. Therefore, the
user can set values in these first 5 E bytes once, and
the settings will persist until the next user change.
This mode is enabled using the Channel Status
Data Buffer Control register.
D to E interrupt occurs
Return
Figure 18. Flowchart for Reading the E Buffer
buffer
Optionally set D to E inhibit
If set, clear D to E inhibit
Read E data
CS8415A
DS470PP3