CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 23

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

8.5
For all bits in this register, a “1” means the associated interrupt condition has occurred at least once since the register
was last read. A ”0” means the associated interrupt condition has NOT occurred since the last reading of the register.
Reading the register resets all bits to 0, unless the interrupt mode is set to level and the interrupt source is still true.
Status bits that are masked off in the associated mask register will always be “0” in this register. This register defaults
to 00h.
DS470PP3
7
0
SOJUST - Justification of SDOUT data relative to OLRCK
Interrupt 1 Status (7h) (Read Only)
SODEL - Delay of SDOUT data relative to OLRCK, for left-justified data formats
SOSPOL - OSCLK clock polarity
SOLRPOL - OLRCK clock polarity
OSLIP - Serial audio output port data slip interrupt
DETC - D to E C-buffer transfer interrupt.
RERR - A receiver error has occurred.
OSLIP
the time slot normally occupied by the P bit is used to indicate the location of the block start,
SDOUT pin only, serial audio output port clock must be derived from the AES3 receiver recov-
ered clock)
1 - Right-justified (master mode only)
1 - MSB of SDOUT data occurs in the second OSCLK period after the OLRCK edge
1 - SDOUT sampled on falling edges of OSCLK
1 - SDOUT data is for the right channel when OLRCK is high
data source, This bit will go high every time a data sample is dropped or repeated.
process.
interrupt.
Default = ‘0’
0 - Left-justified
Default = ‘0’
0 - MSB of SDOUT data occurs in the first OSCLK period after the OLRCK edge
Default = ‘0’
0 - SDOUT sampled on rising edges of OSCLK
Default = ‘0’
0 - SDOUT data is for the left channel when OLRCK is high
When the serial audio output port is in slave mode, and OLRCK is asynchronous to the port
The source for this bit is true during the D to E buffer transfer in the C bit buffer management
The Receiver Error register may be read to determine the nature of the error which caused the
6
5
0
4
0
3
0
DETC
2
1
0
CS8415A
RERR
0
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