CS8415A-CZ Cirrus Logic Inc, CS8415A-CZ Datasheet - Page 30

• Manufacturer Part Number: CS8415A-CZ
• Description: Receiver IC
• Manufacturer: Cirrus Logic Inc

Specifications of CS8415A-CZ

• Driver Case Style: TSSOP
• No. Of Pins: 28
• Mounting Type: Surface Mount
• No. Of Channels: 7
• Peak Reflow Compatible (260 C): No
• Supply Voltage: 5V
• Supply Voltage Max: 5V
• Leaded Process Compatible: No
• Interface Type: Serial
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

9. PIN DESCRIPTION - SOFTWARE MODE
30
SDA/CDOUT
AD0/CS
EMPH
RXP0
RXN0
RXP1
RXP2
RXP3
RXP4
RXP5
RXP6
VA+
AGND
FILT
RST
12
13
14
15
25
26
1
2
3
4
5
6
7
8
9
Serial Control Data I/O (Two-Wire) / Data Out (SPI) (Input/Output) - In Two-Wire mode, SDA is the
control I/O data line. SDA is open drain and requires an external pull-up resistor to VL+. In SPI mode,
CDOUT is the output data from the control port interface on the CS8415A
Address Bit 0 (Two-Wire) / Control Port Chip Select (SPI) (Input/Output) - A falling edge on this pin
puts the CS8415A into SPI control port mode. With no falling edge, the CS8415A defaults to Two-Wire
mode. In Two-Wire mode, AD0 is a chip address pin. In SPI mode, CS is used to enable the control port
interface on the CS8415A
Pre-Emphasis (Output) - EMPH is low when the incoming Channel Status data indicates 50/15 µs pre-
emphasis. EMPH is high when the Channel Status data indicates no pre-emphasis or indicates pre-
emphasis other than 50/15 µs. This is also a start-up option pin, and requires a 47 kΩ resistor to either
VL+ or DGND, which determines the AD2 address bit for the control port in Two-Wire mode
AES3/SPDIF Receiver Port (Input) - Differential line receiver inputs carrying AES3 data. RXP0 may be
used as a single-ended input as part of 7:1 S/PDIF Input MUX. If RXP0 is used in MUX, RXN0 must be
ac coupled to ground.
Additional AES3/SPDIF Receiver Port (Input) - Single-ended receiver inputs carrying AES3 or S/PDIF
digital data. These inputs, along with RXP0, comprise the 7:1 S/PDIF Input Multiplexer and select line
control is accessed using the MUX2:0 bits in the Control 2 register. Please note that any unused inputs
should be tied to ground. See Appendix A for recommended input circuits.
Positive Analog Power (Input) - Positive supply for the analog section. Nominally +5 V. This supply
should be as quiet as possible since noise on this pin will directly affect the jitter performance of the
recovered clock
Analog Ground (Input) - Ground for the analog circuitry in the chip. AGND and DGND should be con-
nected to a common ground area under the chip.
PLL Loop Filter (Output) - An RC network should be connected between this pin and ground. Recom-
mended schematic and component values are given in Figure 5 and Table 1, respectively. Application
note AN159 provides additional resources for the PLL.
Reset (Input) - When RST is low, the CS8415A enters a low power mode and all internal states are
reset. On initial power up, RST must be held low until the power supply is stable, and all input clocks are
stable in frequency and phase. This is particularly true in hardware mode with multiple CS8415A devices
where synchronization between devices is important
SDA/CDOUT
* Pins which remain the same function in all modes.
+ Pins which require a pull up or pull down resistor
AD0/CS
to select the desired startup option.
RMCK
AGND
EMPH
RERR
RXP0
RXN0
RXP1
RXP2
RXP3
FILT
RST
VA+
1
2
3*+
4*
5*
6*
7*
8*
9*
10*
11*
12
13
14
*24
*23
*22
*21
*18
*17
*16
28
27
26
25
20
19
15
RXP6
RXP5
SCL/CCLK
AD1/CDIN
H/S
V +
DGND
OMCK
U
INT
SDOUT
OLRCK
OSCLK
RXP4
L
CS8415A
DS470PP3